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    <title>8-bit MicrocontrollersのトピックRe: What the clock cycle of the HCS08 ?</title>
    <link>https://community.nxp.com/t5/8-bit-Microcontrollers/What-the-clock-cycle-of-the-HCS08/m-p/285974#M20382</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Henry,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;It's good practice to trim internal clock in the application as it can vary in frequency from part to part by as much as ±25% due to processing variations&lt;/P&gt;&lt;P&gt;in manufacturing if leave it untrimmed. We have an application note to explain that.&lt;/P&gt;&lt;P&gt;&lt;A href="http://cache.freescale.com/files/microcontrollers/doc/app_note/AN2496.pdf"&gt;http://cache.freescale.com/files/microcontrollers/doc/app_note/AN2496.pdf&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Hope it will be helpful.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;B.R&lt;/P&gt;&lt;P&gt;XWP&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 24 Jul 2013 02:53:19 GMT</pubDate>
    <dc:creator>weapon</dc:creator>
    <dc:date>2013-07-24T02:53:19Z</dc:date>
    <item>
      <title>What the clock cycle of the HCS08 ?</title>
      <link>https://community.nxp.com/t5/8-bit-Microcontrollers/What-the-clock-cycle-of-the-HCS08/m-p/285971#M20379</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;From the application note "M68HC08 to HCS08 Transition - AN2717", it stated that:&lt;/P&gt;&lt;P&gt;" The M68HC08 CPU clock is equal to the bus clock. The HCS08 CPU clock is twice the speed of the bus&lt;/P&gt;&lt;P&gt;clock. A typical HCS08 has a maximum bus speed of 20 MHz and a maximum CPU speed of 40 MHz.&lt;/P&gt;&lt;P&gt;The documented cycle times for the CPU instructions are still referenced to bus cycles."&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Now I from the datasheet of the HCS08 (SH8), there is a term called the BUSCLK:&lt;/P&gt;&lt;P&gt;BUSCLK — The frequency of the bus is always half of ICSOUT.&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Then I program the ICS to use the FEI mode, and by default, the FLL should output 1024 x 31.25kHz to 39.0625kHz = 32 MHz to 40 MHz for the ICSOUT,&lt;/P&gt;&lt;P&gt;so by default, the BUSCLK should be 16 to 20 MHz.&amp;nbsp; This looks fine and match with the previous statement in the application note.&amp;nbsp; But then, when I write&lt;/P&gt;&lt;P&gt;the following program and measure PORTA bit 0 with a scope, I only got 680 kHz output.&amp;nbsp; 680 x 13 = about 8 MHz.&amp;nbsp; So this obviously does not match with&lt;/P&gt;&lt;P&gt;what is stated in the application note.&amp;nbsp; The listed instruction cycle time listed in the assembly instruction table seems to be twice that of the BUSCLK.&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;DIV class="j-rte-table"&gt;&lt;TABLE&gt;&lt;TBODY&gt;&lt;TR&gt;&lt;TD style=""&gt;&lt;/TD&gt;&lt;TD style=""&gt;asm ("&amp;nbsp; BSET 0,0x00000000 ");&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;/TD&gt;&lt;TD style=""&gt;// 5 cycles.&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD style=""&gt;&lt;/TD&gt;&lt;TD style=""&gt;asm ("&amp;nbsp; BCLR 0,0x00000000 ");&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;/TD&gt;&lt;TD style=""&gt;// 5 cycles.&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD style=""&gt;&lt;/TD&gt;&lt;TD style=""&gt;asm ("&amp;nbsp; BRA&amp;nbsp; *-4&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; ");&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;/TD&gt;&lt;TD style=""&gt;// 3 cycles.&lt;/TD&gt;&lt;/TR&gt;&lt;/TBODY&gt;&lt;/TABLE&gt;&lt;/DIV&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Please tell me how all these "clock cycles" are related, as it seems very confusing.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 23 Jul 2013 09:52:57 GMT</pubDate>
      <guid>https://community.nxp.com/t5/8-bit-Microcontrollers/What-the-clock-cycle-of-the-HCS08/m-p/285971#M20379</guid>
      <dc:creator>HYIU</dc:creator>
      <dc:date>2013-07-23T09:52:57Z</dc:date>
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    <item>
      <title>Re: What the clock cycle of the HCS08 ?</title>
      <link>https://community.nxp.com/t5/8-bit-Microcontrollers/What-the-clock-cycle-of-the-HCS08/m-p/285972#M20380</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Henry,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I'm not sure if this is relevant to you but there is a register in the ICS that controls the BUSCLK division further to the standard divide by 2. If this register were set to divide it by 2 again then you'd see 8MHz (with an untrimmed reference clock).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Hope this helps.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Ian&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 23 Jul 2013 14:28:30 GMT</pubDate>
      <guid>https://community.nxp.com/t5/8-bit-Microcontrollers/What-the-clock-cycle-of-the-HCS08/m-p/285972#M20380</guid>
      <dc:creator>iansmusical</dc:creator>
      <dc:date>2013-07-23T14:28:30Z</dc:date>
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    <item>
      <title>Re: What the clock cycle of the HCS08 ?</title>
      <link>https://community.nxp.com/t5/8-bit-Microcontrollers/What-the-clock-cycle-of-the-HCS08/m-p/285973#M20381</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Ian,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks a lot for your help.&amp;nbsp; After I set the ICS BDIV to divide by 1, the CPU instruction clock cycle is now the same as the BUSCLK at 16 MHz.&lt;/P&gt;&lt;P&gt;But I realized that I can only do this after I correctly set the trim value (ICSTRM).&amp;nbsp; Otherwise the clock cycle might exceed the maximum speed specification.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;BR - Henry&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 24 Jul 2013 00:59:49 GMT</pubDate>
      <guid>https://community.nxp.com/t5/8-bit-Microcontrollers/What-the-clock-cycle-of-the-HCS08/m-p/285973#M20381</guid>
      <dc:creator>HYIU</dc:creator>
      <dc:date>2013-07-24T00:59:49Z</dc:date>
    </item>
    <item>
      <title>Re: What the clock cycle of the HCS08 ?</title>
      <link>https://community.nxp.com/t5/8-bit-Microcontrollers/What-the-clock-cycle-of-the-HCS08/m-p/285974#M20382</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Henry,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;It's good practice to trim internal clock in the application as it can vary in frequency from part to part by as much as ±25% due to processing variations&lt;/P&gt;&lt;P&gt;in manufacturing if leave it untrimmed. We have an application note to explain that.&lt;/P&gt;&lt;P&gt;&lt;A href="http://cache.freescale.com/files/microcontrollers/doc/app_note/AN2496.pdf"&gt;http://cache.freescale.com/files/microcontrollers/doc/app_note/AN2496.pdf&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Hope it will be helpful.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;B.R&lt;/P&gt;&lt;P&gt;XWP&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 24 Jul 2013 02:53:19 GMT</pubDate>
      <guid>https://community.nxp.com/t5/8-bit-Microcontrollers/What-the-clock-cycle-of-the-HCS08/m-p/285974#M20382</guid>
      <dc:creator>weapon</dc:creator>
      <dc:date>2013-07-24T02:53:19Z</dc:date>
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