topic Re: ADC IN DEMO9S08QG8 in 8-bit Microcontrollers

ADC IN DEMO9S08QG8

mmm — Wed, 10 Dec 2008 23:27:03 GMT

I want to do an ADC using the demo. To check that it converts, I have done this program, where the input channel is connected to the port B, pin 7 output:

(...)
                mov #$80,PTBDD   ;port B, pin 7=1
init_adc:   mov #$40,ADCSC1
                mov #$00,ADCSC2
        mov #$98,ADCCFG
                mov #$01,APCTL1


wait:      lda ADCSC1                              ; waits for bit COCO=1
             and #80h
             cbeqa #80h, converted
            jmp wait


converted: lda ADCRH
                 and #03h
                 sta sumh
             lda    ADCRL
          sta suml

(...)

I've tried, but it doesn't work, it doesn't start converting.
Can someone help me? Where is the mistake?

Re: ADC IN DEMO9S08QG8

tonyp — Thu, 11 Dec 2008 00:37:31 GMT

Several problems without looking too deeply.

Do not write to the APCTL1 register (not sure if it matters in this case). The reset default should be OK.

Write to ADCCFG first to "enable" the A/D subsystem. Not really enable, but you must configure dividers before you start a conversion rather than during one.

The value $40 turns on interrupts. But you use polling, so make up your mind which you want, interrupt-driven or polled mode.

Write to the ADCSC1 (with the channel number, channel zero in your case, correct?) last.

Also, you can optimize the check for COCO with the BPL instruction.

Wait tst ADCSC1
bpl Wait

Also, you do not need the AND #3 instruction because the remaining bits are always zero.

Re: ADC IN DEMO9S08QG8

mmm — Thu, 11 Dec 2008 00:43:00 GMT

I've made the changes you told, but still it doesn't work; I realize that the bit ADACT (ADCSC2 bit 7) is always 0.

(...)
             mov #$80,PTBDD
init_adc:      mov #$98,ADCCFG
                   mov #$01,APCTL1
   mov #$00,ADCSC2
                   mov #$00,ADCSC1


wait:    tst ADCSC1
           bpl wait


conv:      lda ADCRH
           sta sumh
           lda    ADCRL
           sta suml

(....)

Re: ADC IN DEMO9S08QG8

tonyp — Thu, 11 Dec 2008 00:51:16 GMT

Do you also make sure this holds true?

Whichever clock is selected, its frequency must fall within the specified frequency range for ADCK. If the
available clocks are too slow, the ADC will not perform according to specifications. If the available clocks are too fast, then the clock must be divided to the appropriate frequency. This divider is specified by the
ADIV bits and can be divide-by 1, 2, 4, or 8.

Message Edited by tonyp on 2008-12-10 06:52 PM