LC60: LVD resets MCU while the module is closed

BasePointer — Mon, 24 Mar 2008 15:41:48 GMT

Hi,

// LVDF Low-Voltage Detect Flag
// LVDACK Low-Voltage Detect Acknowledge
// LVDIE Hardware interrupt disabled (use polling).
// LVDRE Force an MCU reset when LVDF = 1.
// LVDSE Low-voltage detect disabled during stop mode.
// LVDE LVD logic disabled.
// BGBE Bandgap Buffer disabled
SPMSC1 = 0b01010000;

// PDC Power down modes are disabled.
SPMSC2 = 0b00000001; // stop3

// LVDV Low trip point selected (VLVD = VLVDL).
// LVWV Low trip point selected (VLVW = VLVWL).
SPMSC3 = 0b01000000;

The setting above causes MCU to reset with POR and LVD bit in SRS at mass production (ratio: 0.8%). I'm disabled bandgap buffer and LVD logic. I sometimes enable bandgap buffer to measure some external voltage and disable it immediately again. But never enable LVD logic.

Is that possible?

10x,

BP.

Re: LC60: LVD resets MCU while the module is closed

BasePointer — Mon, 24 Mar 2008 19:18:50 GMT

Hi,

I wonder what is the mean of SRS register when it is equal to

0b10000000 -> only POR bit set

0b00000010 -> only LVD bits set

0b10000010 -> POR and LVD bits set *****

When I receive a reset with POR and LVD bits set in SRS, RAM content is still valid.

* The datasheet says that minimum RAM retention supply voltage is 1.0V.

* LVD threshold-low range is 1.76V-1.98V

* What is POR voltage (when does POR bit be set)?

* What is re-arm voltage indicated in the datasheet?

How can I take resets as POR and LVD bit set but with valid ram content?

Regards,

BP.

Message Edited by BasePointer on 2008-03-24 02:22 PM

topic Re: LC60: LVD resets MCU while the module is closed in 8-bit Microcontrollers

LC60: LVD resets MCU while the module is closed

Re: LC60: LVD resets MCU while the module is closed