8-bit Microcontrollers中的主题 Re: regarding PLL lOCK in HCS08

regarding PLL lOCK in HCS08

ramabh — Tue, 18 Mar 2008 12:52:35 GMT

I have a question regarding the PLL inside the MC9S08DZ60.

We are performing some temperature tests on modules built using these processors and we are seeing failures at -40 degC. We are using an external 16MHz crystal as the clock source to generate 20MHz bus clock using the PLL.

When we analysed the problem we found that the PLL is losing lock when we reduce the temperature from room temp to -40 degC. Also, when we do a power cycle at -40 degC, we find that the PLL fails to lock. We also found that when we try power cycle at -40 degC, the processor transitions from FEI->FBE->BLPE mode and fails at a step where it waits for PLL to lock (we wait for 2.5ms for the PLL to lock).

What could be the reason for the PLL to lose lock at -40 degC? Also why is the PLL failing to lock when we do a power cycle at -40 degC?

Re: regarding PLL lOCK in HCS08

BasePointer — Tue, 18 Mar 2008 13:45:18 GMT

Hi,

- Does your crystal have extended operating temperature range (-40C / +85C) ? Most crystals have not.

- If you cool the crystal and the MCU, input gain of the MCU for the crystal will rise significantly. That may cause crystal to overdrive. You should check oscilator amplitude at low temperatures.

You may want to see application note AN849: Basic PICmicro® Oscillator Design from the microchip's web site.

Regards,

BP.

Re: regarding PLL lOCK in HCS08

bigmac — Tue, 18 Mar 2008 13:58:47 GMT

Hello,

Does the external crystal continue to oscillate at -40C? Can you observe a waveform at the crystal pins during low temperature operation? Check that you have the high gain setting (HGO = 1). If you happened to have a low gain setting, the upper limit for the crystal would be 8 MHz.

If in any doubt about the crystal continuing to oscillate, you might try an oscillator module, at least for the purpose of testing and verification.

Using a 16MHz crystal, and with a PLL reference range of 1 - 2MHz, there are two potential settings for RDIV. With each divisor possibility resulting in a reference frequency at each extreme of the allowable range. You might try the alternative RDIV setting to what you are currently using, and see if this makes any difference. You might also try an alternative crystal frequency that can produce a reference frequency at the centre of the range.

Regards,

Mac

Message Edited by bigmac on 2008-03-18 06:01 PM

Re: regarding PLL lOCK in HCS08

ramabh — Tue, 18 Mar 2008 15:58:11 GMT

we are using good crystal which works from -40 to 85 C

Even we tried debugging this case by giving signal input from signal generator with the processor configured for external clock input,But still controller is lossing lock at -40C

we tested around 10 controllers ,Not all controllers are failing at -40 ,only 1 or 2 are failing.

whther it may be controller problem????????????

Re: regarding PLL lOCK in HCS08

bigmac — Tue, 18 Mar 2008 19:02:22 GMT

See if you still have the locking problem for a 12MHz crystal, and a reference division of 8. This is likely to mean that the phase detector within the PLL will operate closer to the centre of its range.

Mac

Re: regarding PLL lOCK in HCS08

BasePointer — Tue, 18 Mar 2008 19:10:05 GMT

Ficgout = fext * P * N / R

Tell your N and R parameters.

Re: regarding PLL lOCK in HCS08

ramabh — Tue, 18 Mar 2008 19:16:23 GMT

MCGOUT = (16 / 16 * 40) = 40 MHZ

so busclk = 20 MHZ

Re: regarding PLL lOCK in HCS08

BasePointer — Wed, 19 Mar 2008 01:37:58 GMT

Hi,

Did you try RDIV = 8, VDIV = 20 -> (16Mhz/8)*20 = 40Mhz?

It may help you. I think your settings 16/16*40 should also work.

Good luck,

BP.

Re: regarding PLL lOCK in HCS08

JohnBarber — Fri, 04 Apr 2008 12:32:28 GMT

Hi,

how did this end up?

I have the same problem, I'm using a 4 MHz crystal which is divided down to a 2 MHz reference to the PLL. The PLL then multiplies the reference to 40 MHz. The output bus frequency is then 20 MHz.

The PLL does not lock in -40C.

We noticed a positive effect when we changed from 1 MHz reference to 2 MHz reference. But the problem still remains on some controllers.

I have a question about this HGO bit. What does it do? Does this bit affect the PLL loop gain?

/John

Re: regarding PLL lOCK in HCS08

ramabh — Fri, 04 Apr 2008 12:42:25 GMT

some masksets of Freescale are having this type of problem.You can directly contact freescale support team to know more.

HGO bit must be set to 1 for high gain operation.That provides a higher amplitude ,more robust crstal drive.