8-bit Microcontrollers中的主题 Re: Logic Level Translation

Logic Level Translation - 68HC11F1

Bob1 — Wed, 24 Sep 2008 02:54:30 GMT

Logic Level Translation Question Regarding the 68HC11F1

The HC11’s minimum high voltage level input voltage is VDD * 0.7 = 3.5V. Most SRAM’s and UART’s guarantee no less than 2.4 volts output as a logic high, but in some cases are still compatible as their outputs are above 3.5 volts anyway.

Does anyone have any thoughts, suggestions, or experience using a chip such as a 74HCT245, or the like, between the HC11 and the data bus as a level translator? I was thinking about using the R/W line for control.

Thanks,
Bob1

Added p/n to subject.

Message Edited by NLFSJ on 2008-09-24 01:34 PM

Re: Logic Level Translation

bigmac — Wed, 24 Sep 2008 12:32:29 GMT

Hello Bob1,

In this case I don't think it would be necessary to use a level translator. For devices that have a "true" TTL output arrangement, simply providing a pull-up resistor (perhaps 2k2 or 4k7) should increase their output level above the minimum input threshold for the MCU.

As you have observed, many devices have CMOS output circuits that meet the threshold requirements. In these cases, the extra pullup will do no harm provided the MCU can handle the extra sink current -usually no problem with the values that I suggested.

Regards,

Mac

Re: Logic Level Translation

Andrey — Wed, 24 Sep 2008 20:22:37 GMT

If you still want to go the buffer route you can use 74HCT125 for MCU out (tx) or 74LCX125 for MCU in (rx)

Re: Logic Level Translation

Bob1 — Wed, 24 Sep 2008 21:28:46 GMT

Thank you Mac and Andrey for your suggestions.

I have not determined which route to pursue. At this time I am experimenting with pull-up resistors on a working system, which has with a few “2.4 volt chips” installed.

It’s difficult to judge the effects of pull-up resistors while looking at a data signal with a scope, but I don’t think a 3.3K contributes to a measurable change on the high levels. Some are between 3.5 and 4 volts. Others are very near 5 volts. And its difficult to know which signal is coming from where. However, it does seem
to pull up the floor of the signal data stream, which I guess represents the time when the data buss is in a high impedance state? At any rate it does not seem to have a negative effect on system performance – it still runs.

Of course the goal is to design a system that is as reliable as possible. So the research goes on.

I welcome any additional thoughts.

Best regards,
Bob

Re: Logic Level Translation

bigmac — Wed, 24 Sep 2008 22:58:55 GMT

Hello Bob1,

Bob1 wrote:
I have not determined which route to pursue. At this time I am experimenting with pull-up resistors on a working system, which has with a few “2.4 volt chips” installed.

It’s difficult to judge the effects of pull-up resistors while looking at a data signal with a scope, but I don’t think a 3.3K contributes to a measurable change on the high levels. Some are between 3.5 and 4 volts. Others are very near 5 volts.

Does your MCU operate with a Vdd of 5 volts and the SRAM with a Vdd of 2.4 volts? If this is so, you are attempting to send a 2.4 volt CMOS output to the MCU. This is a totally different issue, and pullup resistors not work.

For both-way operation of the data bus, the use of the HCT 245 would give the following requirements -

The HCT device would require Vdd of 5 volts.
For the SRAM-to-MCU data direction, operation should be OK since the minimum allowable logic high input level is 2.0 volts.
For the MCU-to-SRAM data direction, a 5 volt CMOS output would be applied to the memory device. Unless the device is specified as having "5 volt compatible inputs", this could be a problem.

For non-compliant inputs, a series resistor to limit the injection current into the input of the memory device may be possible, but this might introduce operating speed limitations. The injection current would need to be limited to a quite low value - check the specification for the memory device, and keep well below the maximum limit for a single input (consider how many input lines may simultaneously have injection current). A 4k7 series resistor should limit the current to about 0.4mA.

For the address bus and other unidirectional control lines you may well be able to us a suitable voltage divider to halve the voltage ouput from the MCU (perhaps a pair of 4k7 resistors for each input).

Regards,

Mac

Message Edited by bigmac on 2008-09-25 02:03 AM

Re: Logic Level Translation

Bob1 — Wed, 24 Sep 2008 23:19:11 GMT

Hi Mac,

Thank you again for the information. Your are obviously very knowledgeable on this subject.

These are all 5-volt chips. I referred to some of them as “2.4 volt chips” because that is their minimum high output rating. I apologize for the confusion.

I guess the crux of the matter is that I’m concerned about this issue of using chips that have a minimum high level of 2.4 volts with this MCU that expects 3.5 volts for a high. They seem to work today, but what if someday they begin to live down (so to speak) to their worse case specification?
I need to determine if this is a valid concern.

Regards,
Bob

Re: Logic Level Translation

Andrey — Thu, 25 Sep 2008 00:13:49 GMT

Bob1 wrote:
but what if someday they begin to live down (so to speak) to their worse case specification?
I need to determine if this is a valid concern.

Regards,
Bob

If both of them are operating on the same level then you don't need anything, this should not occur.

Re: Logic Level Translation

bigmac — Thu, 25 Sep 2008 00:45:36 GMT

Hello Bob,

If the memory device uses a standard CMOS output arrangement, the no load output high voltage should be very close to Vdd. I think you will find that the minimum output voltage specified by the manufacturer assumes that Vdd is on the low side of its tolerance (maybe 4.5 volts), and a load is present so that the output must source a defined amount of current (perhaps a milliamp or two), all for a worst case device with the highest output resistance.

For the MCU, the pin input current should only be a few microamps, so in practice, should be close to the no load case for the memory device. If the no load output high voltage is not very close to Vdd, it is not a standard CMOS output arrangement. See if a graph of typical output voltage versus source current is included in the datasheet.

Finally, if the MCU has internal pullups (not sure about the HC11), leave them enabled. It may not help much, but it should do no harm.

Regards,

Mac

Re: Logic Level Translation

Bob1 — Thu, 25 Sep 2008 01:52:19 GMT

Hello Mac,

After looking again at the data sheet, I tend to agree.
I was overlooking the fact that 4.5 volts was used for the test Vdd.
As long as my power supply stays near 5 volts, and the load current is within reason then I should be OK.
I do not believe that the HC11 has internal pull-ups, so I am considering adding pads for them on a new design just in case they are needed in the future.

I appreciate your time and effort in supplying such a thorough response.

Regards,
Bob

Re: Logic Level Translation

RogerSchaefer — Thu, 25 Sep 2008 09:59:49 GMT

You may want to go to the PMB website http://www.pmb.co.nz/ then to the page on the CPU_1A1 and download the Circuit Diagram. I have used many of the CPU_1A1 and they work well.

Roger

Re: Logic Level Translation

Bob1 — Thu, 25 Sep 2008 19:58:56 GMT

Hello Roger,

Thank you for the input.

Mac has already satisfied me with the minimum high logic level issue, but I had a look at the PMB design anyway. It looks very clean and straight forward, and its an interesting idea of making the MCU module pluggable.

The 32K of RAM is questionable. It has 32K on board, but I suspect that only about 24,576 bytes would be available for use. Nevertheless, I like the design.

Thanks again!

Regards,
Bob