topic Re: MC9S08RE16- need two timers in 8-bit Microcontrollers

MC9S08RE16- need two timers

stevec — Tue, 09 Sep 2008 21:04:59 GMT

I am running a 1mS timer under interrupt as a system clock. I need to independantly determine a fixed 62.5uS timer to achieve a 16kHz speech output sample rate i.e start 62.5uS timer, output to DAC, wait for timer to time out. How can I achieve this with only the one timer module (if at all).

Re: MC9S08RE16- need two timers

bigmac — Wed, 10 Sep 2008 10:22:35 GMT

Hello,

It is not clear how you have already configured the timer for your 1ms tick. However, there would appear to be a couple of alternatives, using either one or two channels of the TPM module, in output compare mode. In both cases, the TPM modulo setting should remain at its default, with a free-running counter.

The first alternative would be to use separate channels for each of the intervals. When an interrupt occurs following each output compare event, simply add the number of increments corresponding to the required interval to the current channel value.

The second possibility would require only a single TPM channel, again using output compare mode (normally interrupt only configuration), to generate an interrupt every 62.5 microseconds. Then within the ISR, increment a count value. One in every 16 interrupts would then correspond with the `1ms tick.

count++; // Every 62.5us

if (!(count & 0x0F))

tick = 1; // Every 1ms

Regards,

Mac

Message Edited by bigmac on 2008-09-10 01:34 PM

Re: MC9S08RE16- need two timers

stevec — Wed, 10 Sep 2008 15:12:47 GMT

Thanks Bigmac,

So I can not run two independant timers. I see that now as there is only one counter. I was trying to reduce interrupt processing time as my speech output routine takes 47 uS. I don't have much time left within the 62.5 uS sample period to do other things like switch debounce. I may have to review whether I go back to the AT89F51 I was using before (which has 2 timers). When I chose this particular HCS08 chip I was mislead by the manual into thinking that the CPU executed instructions at a higher rate (xtal freq rather than xtal freq/2) so I though I had lots of clock cycles to get things done in.
I will look at your suggestions however and see which has the lowest overhead.

Re: MC9S08RE16- need two timers

bigmac — Wed, 10 Sep 2008 22:26:25 GMT

Hello,

To avoid the additional complexity (and execution cycles) of handling nested interrupts, it sounds like the 1ms tick should be derived within the 62.5 us interrupt routine. This way you will avoid the potential for the additional overhead of a second interrupt to delay the priority interrupt.

I assume you would be using the maximum bus frequency of 8MHz, with 500 bus cycles between successive interrupts. You may need to use inline assembly code for the ISR to minimize the number cycles required.

In pure assembly code, the minimum overhead to enter the interrupt, update the OC value, clear the interrupt flag, and exit the interrupt would amount to about 40 cycles (5 us). Here, I assume a prescale value of 4 for the TPM. To further set a 1ms tick flag, for eventual processing as a background task, would need an additional 13 - 17 cycles within the ISR. With this optimised code, the total overhead should amount to about 7.1 us. Obviously, this would not leave many cycles for background processing tasks.

For the purpose of the calculation, here is the assembly code that I assumed -

ISR_TPMCH0: ; [11] Entry to ISR

pshh ; [2]

ldhx TPMC0V ; [4] Update TPM channel

aix #125 ; [2]

sthx TPMC0V ; [4]

inc COUNT ; [5] Global variable in zero page

lda COUNT ; [3]

and #$0F ; [2] Mask low nybble

bne BR1 ; [3] Branch if not timeout

mov #1,TICK ; [4] Global variable in zero page

BR1:

; Other code here

bclr CH0F,TPMC0SC ; [5] Clear flag

pulh ; [3]

rti ; [9]

Could there be a possibility that your speech output routine would benefit from the use of assembly code (if you are not already doing so)?

Regards,

Mac