8-bit MicrocontrollersのトピックRe: Single wired - half duplex SCI management problem

Single wired - half duplex SCI management problem

utall — Thu, 28 Aug 2008 14:20:50 GMT

Hi all,
I've a problem with SCI module. I use the single wired communication (LOOPS = Rsrc=1) and I'd like to enable the transmission only when I need to transmit. How can I know when the tx (or rx) is ready? How many time does it take to become usable?
Thanks. Have a nice day.

Andrea

Re: Single wired - half duplex SCI management problem - QG4

bigmac — Thu, 28 Aug 2008 20:28:56 GMT

Hello Andrea,

You do not say which device you are using. However, I will assume a HCS08 device, and that you are controlling the transmission direction using the SCIC3_TXDIR control bit.

There are two possibilities. The first one is that the SCIC2_TE bit remains continuously active, and with the following sequence of events required to complete a transmission.

Set TXDIR bit to 1 for send operation.
Write first send character to SCID register.
If further characters to be sent, wait until TDRE flag bit is set before writing each subsequent character.
After final send character is written, wait until TC flag bit becomes set.
Set TXDIR bit to 0 for further receive operation.

The first send character should commence immediately after the first character is written to SCID.

The second possibility is that the TE control bit is set to 1 immediately preceeding step 1 above, and is then cleared to 0 following step 5. This will cause an additional idle character to be sent prior to the first send character, thus delaying the commencement of the first send character by the byte transmission period.

Regards,

Mac

Message Edited by bigmac on 2008-08-28 11:31 PM

Message Edited by NLFSJ on 2008-08-30 10:28 AM

Re: Single wired - half duplex SCI management problem

utall — Thu, 28 Aug 2008 21:05:47 GMT

Hello Mac,
Thanks for your answer.
Yes, I'm using a QG4 device so the S08 micro family.

My greatest problem is that when I set TE to enable the tx I've to wait for a while before start sending data. Is this normal? This time is around 100ms (!!!).
BTW the operations I implemented follow exactly your list (first case).

Thanks for your patience.
Bye

Andrea

Re: Single wired - half duplex SCI management problem

bigmac — Thu, 28 Aug 2008 21:41:19 GMT

Hello Andrea,

When TE is first set to 1, an idle character is automatically loaded to the SCI send register, as previously mentioned. The sending of this character is transparent to the receiver, but must be completed before the first "real" character is sent. The delay will depend on the baud rate you are using, and should be equal to ten bit periods (for 8 data bits).

To avoid this delay, simply leave TE set to 1. Of course the idle character will be sent once, when TE is first set during initialisation, but will not occur with normal communications.

During the send time for the idle character, it should still be possible to queue the first character within the send buffer, to be sent immediately following the completion of the idle character.

The datasheet for the QG8 device should cover this in some detail.

Regards,

Mac

Re: Single wired - half duplex SCI management problem

utall — Thu, 28 Aug 2008 22:13:04 GMT

Ok, there was a problem in the serial cable. It seems to be ok now. Thanks a lot.
Bye

Andrea