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    <title>topic pending Interrupt of HCS08 in 8-bit Microcontrollers</title>
    <link>https://community.nxp.com/t5/8-bit-Microcontrollers/pending-Interrupt-of-HCS08/m-p/181035#M13133</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi All,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I have a question about interrupt prioritiy. Suppose there are two interrupts, IntA and IntB, IntA has a high interrupt priority than IntB. What happen if IntB occurs in the ISR of IntA? Will IntB be ignored or served after the ISR of IntA?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;CPkwok&amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 14 May 2009 11:28:34 GMT</pubDate>
    <dc:creator>left</dc:creator>
    <dc:date>2009-05-14T11:28:34Z</dc:date>
    <item>
      <title>pending Interrupt of HCS08</title>
      <link>https://community.nxp.com/t5/8-bit-Microcontrollers/pending-Interrupt-of-HCS08/m-p/181035#M13133</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi All,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I have a question about interrupt prioritiy. Suppose there are two interrupts, IntA and IntB, IntA has a high interrupt priority than IntB. What happen if IntB occurs in the ISR of IntA? Will IntB be ignored or served after the ISR of IntA?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;CPkwok&amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 14 May 2009 11:28:34 GMT</pubDate>
      <guid>https://community.nxp.com/t5/8-bit-Microcontrollers/pending-Interrupt-of-HCS08/m-p/181035#M13133</guid>
      <dc:creator>left</dc:creator>
      <dc:date>2009-05-14T11:28:34Z</dc:date>
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    <item>
      <title>Re: pending Interrupt of HCS08</title>
      <link>https://community.nxp.com/t5/8-bit-Microcontrollers/pending-Interrupt-of-HCS08/m-p/181036#M13134</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello CPkwok, and welcome to the forum.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;During execution of an ISR, by default further interrupts are globally disabled until the current ISR is completed.&amp;nbsp; However, the various interrupt flags controlled by each hardware peripheral may be set during this period, and the interrupt will become pending.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;When the current ISR finishes, the highest priority pending interrupt will next be processed.&amp;nbsp; No interrupt events should be lost.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Mac&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 14 May 2009 13:06:38 GMT</pubDate>
      <guid>https://community.nxp.com/t5/8-bit-Microcontrollers/pending-Interrupt-of-HCS08/m-p/181036#M13134</guid>
      <dc:creator>bigmac</dc:creator>
      <dc:date>2009-05-14T13:06:38Z</dc:date>
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