<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: QE128 64 pin has two MISO1, SS1 in 8-bit Microcontrollers</title>
    <link>https://community.nxp.com/t5/8-bit-Microcontrollers/QE128-64-pin-has-two-MISO1-SS1/m-p/177845#M12586</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;No surprises here.&amp;nbsp; From the manual:&lt;BR /&gt;&lt;BR /&gt;"SPI1 pins (SS1, MISO1, MOSI1, and SPSCK1) can be repositioned using SPI1PS in SOPT2.&lt;BR /&gt;Default locations are PTB5, PTB4, PTB3, and PTB2."&lt;BR /&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Sat, 02 Aug 2008 17:51:50 GMT</pubDate>
    <dc:creator>tonyp</dc:creator>
    <dc:date>2008-08-02T17:51:50Z</dc:date>
    <item>
      <title>QE128 64 pin has two MISO1, SS1</title>
      <link>https://community.nxp.com/t5/8-bit-Microcontrollers/QE128-64-pin-has-two-MISO1-SS1/m-p/177844#M12585</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt; &lt;/DIV&gt;&lt;DIV&gt;Hi,&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;QE128 64 pin&amp;nbsp;has many pins for SPI1 module.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;for&amp;nbsp;SPI1&lt;/DIV&gt;&lt;DIV&gt;PTE0/TPM2CLK/SPSCK1 (pin 60)&lt;BR /&gt;PTE1/MOSI1 (pin 59)&lt;BR /&gt;PTE2/MISO1 (pin 54)&lt;BR /&gt;PTE3/SS1 (pin 53)&lt;/DIV&gt;&lt;DIV&gt;and&lt;/DIV&gt;&lt;DIV&gt;PTB2/KBI1P6/SPSCK1/ADP6 (pin 32)&lt;BR /&gt;PTB3/KBI1P7/MOSI1/ADP7 (pin 31)&lt;BR /&gt;PTB4/TPM2CH1/MISO1 (pin 19)&lt;BR /&gt;PTB5/TPM1CH1/SS1 (pin 18)&lt;/DIV&gt;&lt;DIV&gt;---------------------------------&lt;/DIV&gt;&lt;DIV&gt;for SPI2&lt;/DIV&gt;&lt;DIV&gt;PTD0/KBI2P0/SPSCK2 (pin 2)&lt;BR /&gt;PTD1/KBI2P1/MOSI2 (pin 1)&lt;BR /&gt;PTD2/KBI2P2/MISO2 (pin 46)&lt;BR /&gt;PTD3/KBI2P3/SS2 (pin 45)&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;I wonder mean of shared pins.&lt;/DIV&gt;&lt;DIV&gt;When I enable SPI1 module, which pin will have SPSCK1, PTE0, PTB2 or both?&lt;/DIV&gt;&lt;DIV&gt;If both, I will be lost 4 I/O functionality? This is bad.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Regards,&lt;/DIV&gt;&lt;DIV&gt;BP.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sat, 02 Aug 2008 17:38:23 GMT</pubDate>
      <guid>https://community.nxp.com/t5/8-bit-Microcontrollers/QE128-64-pin-has-two-MISO1-SS1/m-p/177844#M12585</guid>
      <dc:creator>BasePointer</dc:creator>
      <dc:date>2008-08-02T17:38:23Z</dc:date>
    </item>
    <item>
      <title>Re: QE128 64 pin has two MISO1, SS1</title>
      <link>https://community.nxp.com/t5/8-bit-Microcontrollers/QE128-64-pin-has-two-MISO1-SS1/m-p/177845#M12586</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;No surprises here.&amp;nbsp; From the manual:&lt;BR /&gt;&lt;BR /&gt;"SPI1 pins (SS1, MISO1, MOSI1, and SPSCK1) can be repositioned using SPI1PS in SOPT2.&lt;BR /&gt;Default locations are PTB5, PTB4, PTB3, and PTB2."&lt;BR /&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sat, 02 Aug 2008 17:51:50 GMT</pubDate>
      <guid>https://community.nxp.com/t5/8-bit-Microcontrollers/QE128-64-pin-has-two-MISO1-SS1/m-p/177845#M12586</guid>
      <dc:creator>tonyp</dc:creator>
      <dc:date>2008-08-02T17:51:50Z</dc:date>
    </item>
    <item>
      <title>Re: QE128 64 pin has two MISO1, SS1</title>
      <link>https://community.nxp.com/t5/8-bit-Microcontrollers/QE128-64-pin-has-two-MISO1-SS1/m-p/177846#M12587</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;I just saw them,&amp;nbsp;this is a good news &lt;IMG alt=":smileyhappy:" class="emoticon emoticon-smileyhappy" id="smileyhappy" src="http://freescale.i.lithium.com/i/smilies/16x16_smiley-happy.gif" title="Smiley Happy" /&gt; thank you so much tony!&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;SPI1 Pin Select — This bit selects the location of the MOSI1, MISO1, SPSCLK1, and SS1 pins of the SPI1 module.&lt;BR /&gt;0 SPSCLK1 on PTB2, MOSI1 on PTB3, MISO1 on PTB4, and SS1 on PTB5.&lt;BR /&gt;1 SPSCLK1 on PTE0, MOSI1 on PTE1, MISO1 on PTE2, and SS1 on PTE3.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sat, 02 Aug 2008 19:14:14 GMT</pubDate>
      <guid>https://community.nxp.com/t5/8-bit-Microcontrollers/QE128-64-pin-has-two-MISO1-SS1/m-p/177846#M12587</guid>
      <dc:creator>BasePointer</dc:creator>
      <dc:date>2008-08-02T19:14:14Z</dc:date>
    </item>
  </channel>
</rss>

