topic Re: Clock / MCG settings on 9S08DZ60 in 8-bit Microcontrollers

Clock / MCG settings on 9S08DZ60

Tino — Tue, 29 Jul 2008 05:47:48 GMT

Hi together,
I am getting started with 9S08DZ60. I got the demo board and wrote my first program with the CodeWarrior.
I just want to toggle an output pin at max speed. I got it to work but the speed doesn't fit the settings I made.
First I tried with the processor expert. External clock enabled, clock source crystal, 4Mhz, PEE mode, 16MHz PLL output.
But on the oscilloscope I just get 714kHz.
Then I took the example #1 from the datasheet. Then I get about 1.4MHz at the pin. Still not the supposed frequency of 8Mhz.

I am new to the Freescale technology, so maybe I am missing something out here.
The MCG thingy is a bit hard to understand if you are new to it. But I already figured out the basic principle.
At what frequency is the main program running at? MCGOUT or bus frequency?

Thanks in advance,
Tino.

Re: Clock / MCG settings on 9S08DZ60

bigmac — Tue, 29 Jul 2008 08:42:35 GMT

Hello Tino,

The result you are getting would appear to be that which is expected.

A CPU cycle is determined by the bus frequency, rather than MCGOUT - the bus frequency will be a sub-multiple. It appears that your bus frequency is probably 16MHz.

To provide the code for a tight software loop used to toggle an output pin, will require many bus cycles for each passage through the loop. In assembly code, the tightest loop would require 11 cycles for execution of each half period, or 22 cycles for a full period. For example, toggling bit-0 of PTA,

LOOP1:

LDA PTAD ; [3]

EOR #$01 ; [2]

STA PTAD ; [3]

BRA LOOP1 ; [3]

Regards,

Mac

Re: Clock / MCG settings on 9S08DZ60

Tino — Tue, 29 Jul 2008 17:06:00 GMT

Hi Mac,
Now it makes perfectly sense. When I divide my bus frequency by 11 I get exactly what I expect on the oscilloscope.
I should have checked the Instruction set of the mcu and the execution times.

I am used to avr which do this a lot quicker:

LOOP1:

LDA PTAD ; [2]

EOR #$01 ; [1]

STA PTAD ; [2]

BRA LOOP1 ; [1]

= 6 clk

Thanks for your quick answer!
Tino