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    <title>8-bit MicrocontrollersのトピックMC13213 locking  to external clock</title>
    <link>https://community.nxp.com/t5/8-bit-Microcontrollers/MC13213-locking-to-external-clock/m-p/169671#M11260</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;SPAN&gt;Hello,&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I am stuck here with a problem by switching the controller in the MC13213 to the external clock mode with FLL engaged, FEE mode. The device wont lock to the external supplied 32,786kHz clock.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;here is my initialiazation code:&lt;/SPAN&gt;&lt;BR /&gt;&lt;DIV&gt;&lt;DIV class="msg_source_code"&gt;&lt;DIV class="text_smallest"&gt;Code:&lt;/DIV&gt;&lt;PRE&gt;ICGC1_RANGE = 0;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; /* range low. */ICGC1_OSCSTEN = 1;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; /* Osc enabled in off mode. */ICGC1_REFS = 0;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; /* interal ref off&amp;nbsp; */ICGC1_CLKS1 = 1;ICGC1_CLKS0 = 1;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; /*FEE external ref fll engaged */&amp;nbsp;&amp;nbsp; while (!ICGS1_ERCS)&amp;nbsp;&amp;nbsp;&amp;nbsp; /* Wait for external reference to be stable. */&amp;nbsp;&amp;nbsp;&amp;nbsp; __RESET_WATCHDOG();&amp;nbsp; while (!ICGS2_DCOS)&amp;nbsp;&amp;nbsp;&amp;nbsp; /* Wait for external reference to be stable. */&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; __RESET_WATCHDOG();&lt;/PRE&gt;&lt;/DIV&gt;and the controller allways stucks at:&lt;BR /&gt;&lt;PRE&gt;while (!ICGS1_ERCS)&lt;/PRE&gt;&amp;nbsp;the second while loop would be passed if the first is disabled. But anyway if I do so the clocking result is far from the expected behavior. The supplied external clock is stable and the shematic looks like the suggested in the datasheet with CLKO connected to EXTAL and XTAL n.c.&lt;BR /&gt;&lt;BR /&gt;regards&lt;BR /&gt;thomas&lt;BR /&gt;&lt;/DIV&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;DIV&gt; &lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 29 Oct 2020 09:17:46 GMT</pubDate>
    <dc:creator>Thomas_H</dc:creator>
    <dc:date>2020-10-29T09:17:46Z</dc:date>
    <item>
      <title>MC13213 locking  to external clock</title>
      <link>https://community.nxp.com/t5/8-bit-Microcontrollers/MC13213-locking-to-external-clock/m-p/169671#M11260</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;SPAN&gt;Hello,&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I am stuck here with a problem by switching the controller in the MC13213 to the external clock mode with FLL engaged, FEE mode. The device wont lock to the external supplied 32,786kHz clock.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;here is my initialiazation code:&lt;/SPAN&gt;&lt;BR /&gt;&lt;DIV&gt;&lt;DIV class="msg_source_code"&gt;&lt;DIV class="text_smallest"&gt;Code:&lt;/DIV&gt;&lt;PRE&gt;ICGC1_RANGE = 0;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; /* range low. */ICGC1_OSCSTEN = 1;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; /* Osc enabled in off mode. */ICGC1_REFS = 0;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; /* interal ref off&amp;nbsp; */ICGC1_CLKS1 = 1;ICGC1_CLKS0 = 1;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; /*FEE external ref fll engaged */&amp;nbsp;&amp;nbsp; while (!ICGS1_ERCS)&amp;nbsp;&amp;nbsp;&amp;nbsp; /* Wait for external reference to be stable. */&amp;nbsp;&amp;nbsp;&amp;nbsp; __RESET_WATCHDOG();&amp;nbsp; while (!ICGS2_DCOS)&amp;nbsp;&amp;nbsp;&amp;nbsp; /* Wait for external reference to be stable. */&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; __RESET_WATCHDOG();&lt;/PRE&gt;&lt;/DIV&gt;and the controller allways stucks at:&lt;BR /&gt;&lt;PRE&gt;while (!ICGS1_ERCS)&lt;/PRE&gt;&amp;nbsp;the second while loop would be passed if the first is disabled. But anyway if I do so the clocking result is far from the expected behavior. The supplied external clock is stable and the shematic looks like the suggested in the datasheet with CLKO connected to EXTAL and XTAL n.c.&lt;BR /&gt;&lt;BR /&gt;regards&lt;BR /&gt;thomas&lt;BR /&gt;&lt;/DIV&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;DIV&gt; &lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 29 Oct 2020 09:17:46 GMT</pubDate>
      <guid>https://community.nxp.com/t5/8-bit-Microcontrollers/MC13213-locking-to-external-clock/m-p/169671#M11260</guid>
      <dc:creator>Thomas_H</dc:creator>
      <dc:date>2020-10-29T09:17:46Z</dc:date>
    </item>
    <item>
      <title>Re: MC13213 locking  to external clock</title>
      <link>https://community.nxp.com/t5/8-bit-Microcontrollers/MC13213-locking-to-external-clock/m-p/169672#M11261</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;OK. I've found the problem already.&lt;BR /&gt;The CLKS bits have to be set at once otherwise the CPU may be stuck at internal clock and can't switch to external clock until next reset.&lt;BR /&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;BR /&gt;regards&lt;BR /&gt;thomas&lt;BR /&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 03 Jul 2008 18:26:18 GMT</pubDate>
      <guid>https://community.nxp.com/t5/8-bit-Microcontrollers/MC13213-locking-to-external-clock/m-p/169672#M11261</guid>
      <dc:creator>Thomas_H</dc:creator>
      <dc:date>2008-07-03T18:26:18Z</dc:date>
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