topic Re: Not enough information about Supported BIST configurations for S32K396 in SafeAssure Community (Archived)

Not enough information about Supported BIST configurations for S32K396

Berk123 — Wed, 16 Nov 2022 12:46:11 GMT

Hello, so I was wondering on what the differences between BIST_SAFETYBOOT_CFG and BIST_DIAGNOSTIC_CFG is, also if you can provide me with "every single BIST available on the platform" according to the BIST SPD user manual. Thank you!

Re: Not enough information about Supported BIST configurations for S32K396

frantisekdobes — Tue, 22 Nov 2022 12:25:02 GMT

Hello,

the Bist Manager software supports the following selftest configurations on S32K396:

BIST_DIAGNOSTIC_CFG - contains all the M/LBISTs available on the device, i.e. MBIST0 up to 11 and LBIST0
BIST_SAFETYBOOT_CFG – contains MBIST1 up to 11 and LBIST0 (i.e. the same as diagnostic config except that it does not contain MBIST0)

The MBIST and LBIST are documented in HW reference manual, section “49.1.3 STCU2 LBIST/MBIST mapping”.

Best Regards,
Frantisek

Re: Not enough information about Supported BIST configurations for S32K396

Berk123 — Mon, 28 Nov 2022 07:57:39 GMT

Which memory index is connected to the MBIST0? Is it the ones with 0 or are there different ones that are connected to MBIST0?

Re: Not enough information about Supported BIST configurations for S32K396

frantisekdobes — Tue, 29 Nov 2022 14:24:41 GMT

Hello,

the MBIST0 corresponds to "BIST Index"=0 and "BIST Name"=HSE_ROMS. I have checked the HW reference manual and the MBIST0 is not described there so I will provide more details after confirmation from HW team.

Best Regards,

Frantisek

Re: Not enough information about Supported BIST configurations for S32K396

Berk123 — Tue, 29 Nov 2022 14:25:39 GMT

Hi,
I really appreciate your time and effort, that would be very helpful
Regards

Re: Not enough information about Supported BIST configurations for S32K396

Berk123 — Thu, 01 Dec 2022 08:29:32 GMT

Hi,
Any updates from the HW team?
Regards!

Re: Not enough information about Supported BIST configurations for S32K396

frantisekdobes — Thu, 01 Dec 2022 09:49:39 GMT

Hi,

the HW team confirmed that MBIST0 is the HSE_ROMS MBIST. There are memory reliability and retention tests for this ROM and these are part only of BIST_DIAGNOSTIC_CFG. Normally customers run BIST_SAFETYBOOT_CFG which does not contain this MBIST0.

Best Regards,

Frantisek

Re: Not enough information about Supported BIST configurations for S32K396

Berk123 — Thu, 01 Dec 2022 13:15:04 GMT

Hi,
I understand what you guys mean but when using the diagnostic in my code the ECU goes into a power down state instead of a sleeping state, which im trying to figure out why but if it is only memory reliability and retention tests why would it act differently?
Berk

Re: Not enough information about Supported BIST configurations for S32K396

frantisekdobes — Fri, 16 Dec 2022 17:16:45 GMT

Hello @Berk123 ,

to summarize results of investigations we did together: we have seen the same issue in our tests (i.e. selftest failed with STCU WDTOSW bit set which is watchdog timeout). This was caused by not enabled EMAC clock by MC_CGM.MUX_9_DC_0 which is mandatory to run the selftest on EMAC TSN memory (MBIST11) as per this note from HW reference manual:

======================================================
While running MBIST on EMAC timestamp memory, MC_CGM.MUX_9_DC_0[DIV] should be appropriately configured to ensure EMAC_CLK_TS should be at least 1.5 times the AIPS_SLOW_CLK frequency.
======================================================

After enabling the EMAC clock the selftest (both safetyboot and diagnostic) is done correctly without any errors.

Best Regards,
Frantisek