Selection and Isolation Scheme Design of S32K Chip

FXY — Mon, 22 May 2023 14:54:38 GMT

Hi,team

1. Assume that within a CORE of S32K3, we use MPU tools to rank software components into ASIL levels. Which architecture within S32K will result in the above design scheme not meeting the independent requirements of FUSA?

2. Assuming that we have three software components of different security levels, QM, ASILB, ASILD, how many COREs of S32K are recommended?

Re: Selection and Isolation Scheme Design of S32K Chip

aarul — Mon, 05 Jun 2023 08:20:21 GMT

1. On K3, we provide XRDC apart from the core MPU to enable isolation. Without XRDC (and only relying on MPU), it will be difficult to isolate transactions from non-core masters such as ENET/DMA. Also, XRDC provides more flexibility in terms of defining the regions to be protected including those of peripherals.

2. It depends on the performance required. You can even run all three on a single core. Please review the XRDC chapter in RM to know more about how you can perform the isolation between applications running on the same core (esp. around pID).

Regards

-Aarul

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Selection and Isolation Scheme Design of S32K Chip

Re: Selection and Isolation Scheme Design of S32K Chip