S12 / MagniV MicrocontrollersのトピックRe: MC9S12XET256 Timer enable TSCR1

MC9S12XET256 Timer enable TSCR1

hucklim — Wed, 29 Jan 2014 09:17:02 GMT

Hello everyone,

I have a general question. I am using the ECT timer in MC9S12XET256. To enable the timer I set the TSCR1 to 0x80 (setting 1 to the TEN bit).

My question is, if I were to set the timer enable multiple time without disabling the timer in between, like below, is there any side-effect in terms of timer accuracy etc...?

ECT_TSCR1 = 0x80 //enable timer

//do something

ECT_TSCR1 = 0x80

Thanks for replying.

Yours sincerely,

Huck

Re: MC9S12XET256 Timer enable TSCR1

lama — Wed, 29 Jan 2014 14:09:02 GMT

Hi,

writing the same value to the register or memory has no effect neither on the content nor on the accuracy of the timer..

The exception is writing to the interrupt flag status register where interrutp flag 1 is being cleared by writin 1 to the corresponding bits.

For example;

status register is 0B01010101

writing value 0B00000101

will result int the status register's value 0B01010000

Best regards,

Ladislav

Re: MC9S12XET256 Timer enable TSCR1

hucklim — Thu, 30 Jan 2014 07:32:22 GMT

Hello Ladislav,

thanks for the information. Knowing this is good for me so that I can exclude some of the possible source of bugs in my implementation.

Thanks.

Yours sincerely,

Huck

Re: MC9S12XET256 Timer enable TSCR1

lama — Sun, 02 Feb 2014 19:18:13 GMT

I'd like only to add. Never use following code, for example status |= 0B00000101; for clearing status register when you want to clear bit 0 and 2:

The instruction is internally performed as read modify write so the result is:

Let status register is 0B01010101 and you want to clear bit 2 and 0 and you use code as presented above (status |= 0B00000101; ).

Internal procedure performs following:

read : temp = 0B01010101

modify : temp = temp | 0B00000101

write : 0B01010101 -> status

The result is that all bits in the status regfister are cleared. This is standard mistake I have met a lot of times.

So, you wave to write direct number with corresponding bits (bits you want clear) set to 1 to clear them.

Best regards,

Ladislav

Re: MC9S12XET256 Timer enable TSCR1

hucklim — Mon, 03 Feb 2014 07:33:00 GMT

Hello Ladislav,

thanks for the extra tips for clearing the status register. I will surely have to watch out for this.

Yours sincerely,

Huck