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    <title>S12 / MagniV MicrocontrollersのトピックRe: MC9S12XEG EEE repartitioning problem ?</title>
    <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/MC9S12XEG-EEE-repartitioning-problem/m-p/249111#M9654</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;No, there is no such timing limit nor watchdog enabled.&lt;/P&gt;&lt;P&gt;Watchdog will be enabled after initialization of EEPROM done successfully.&lt;/P&gt;&lt;P&gt;after unit programming finished by cyclonPro, CPU won’t start until power off and on the micro.&lt;/P&gt;&lt;P&gt;It means that micro working in normal mode, not special mode. &lt;/P&gt;&lt;P&gt;I think there is no reason for termination partitioning. &lt;/P&gt;&lt;P&gt;It seems that unsecuring micro by cyclone don’t erase address 0x12_0000&amp;nbsp; through 0x12_0007 sometimes (is it possible?).&lt;/P&gt;&lt;P&gt;Failed units (10% I’ve already discussed) has the correct partition but when application writes to buffer RAM, FERSTAT_ERSVIF0 will be set and data won’t transfer to D-flash.&lt;/P&gt;&lt;P&gt;After reprogramming (again unsecure, program &amp;amp; secure) everything going to be alright.&lt;/P&gt;&lt;P&gt;Confusing !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!&lt;/P&gt;&lt;P&gt;&lt;SPAN class="mce_paste_marker"&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 02 Jul 2013 13:57:33 GMT</pubDate>
    <dc:creator>adelantesey</dc:creator>
    <dc:date>2013-07-02T13:57:33Z</dc:date>
    <item>
      <title>MC9S12XEG EEE repartitioning problem ?</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/MC9S12XEG-EEE-repartitioning-problem/m-p/249106#M9649</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;In using EEE of MC9S12XEG128, suppose that there is a wrong partition on D-Flash &amp;amp; Buffer RAM.&lt;/P&gt;&lt;P&gt;Partition-D-Flash command (which is an application level command) wants to reparation D-Flash.&lt;/P&gt;&lt;P&gt;Which command should be launch before Partition-D-Flash command?&lt;/P&gt;&lt;P&gt;Please note that since I’m using &lt;SPAN style="color: red;"&gt;cyclonePro&lt;/SPAN&gt; for programming micro, it is not possible to launch &lt;SPAN style="color: red;"&gt;Erase-All-Block &lt;/SPAN&gt;command (because of micro operating mode). &lt;/P&gt;&lt;P&gt;Please kindly review following initialization function and let me know if there is any problem.&lt;/P&gt;&lt;P&gt;Thank you.&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;bool ETK_boolEEPROMInit(void) &lt;/P&gt;&lt;P&gt;{&lt;/P&gt;&lt;P&gt;&amp;nbsp; int8u dfPart, erPart;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;/P&gt;&lt;P&gt;&amp;nbsp; while(!FSTAT_CCIF);&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp; /* Set clock value */&amp;nbsp; &lt;/P&gt;&lt;P&gt;&amp;nbsp; FCLKDIV&amp;nbsp; = FCLK_DIV_CFG; &lt;/P&gt;&lt;P&gt;&amp;nbsp; while(!FSTAT_CCIF);&lt;/P&gt;&lt;P&gt;&amp;nbsp; if(FCLKDIV != (FSTAT_CCIF_MASK | FCLK_DIV_CFG))&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; return EEPROM_INIT_FAIL;&amp;nbsp; &lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt; LaunchEepromCommand(0,&lt;SPAN style="color: red;"&gt;EEPROM_QUERY&lt;/SPAN&gt;,0,0,0);&lt;/P&gt;&lt;P&gt;&amp;nbsp; if((FSTAT!=FSTAT_CCIF_MASK)||(FERSTAT !=0x00))&amp;nbsp; &lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; return&amp;nbsp; EEPROM_INIT_FAIL;&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp; FCCOBIX = 1;&lt;/P&gt;&lt;P&gt;&amp;nbsp; dfPart = FCCOBLO;&lt;/P&gt;&lt;P&gt;&amp;nbsp; FCCOBIX++;&lt;/P&gt;&lt;P&gt;&amp;nbsp; erPart = FCCOBLO;&lt;/P&gt;&lt;P&gt;&amp;nbsp; if((erPart != EEE_RAM)||(dfPart != DFPART))&lt;/P&gt;&lt;P&gt;&amp;nbsp; {&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; /* EEPROM hasn't been initialized yet */&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; LaunchEepromCommand(2, &lt;SPAN style="color: red;"&gt;PARTITION_D_FLASH&lt;/SPAN&gt;, 0, DFPART, EEE_RAM);&lt;/P&gt;&lt;P&gt; if((FSTAT!=FSTAT_CCIF_MASK)||(FERSTAT !=0x00))&amp;nbsp; &lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; return EEPROM_INIT_FAIL;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; LaunchEepromCommand(0,&lt;SPAN style="color: red;"&gt;EEPROM_QUERY&lt;/SPAN&gt;,0,0,0);&lt;/P&gt;&lt;P&gt; if((FSTAT!=FSTAT_CCIF_MASK)||(FERSTAT !=0x00))&amp;nbsp; &lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; return EEPROM_INIT_FAIL;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; FCCOBIX = 1;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; dfPart = FCCOBLO;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; FCCOBIX++;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; erPart = FCCOBLO;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; if((erPart != EEE_RAM)||(dfPart != DFPART))&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; return EEPROM_INIT_FAIL; &lt;/P&gt;&lt;P&gt;&amp;nbsp; }&lt;/P&gt;&lt;P&gt;&amp;nbsp; LaunchEepromCommand(0,&lt;SPAN style="color: red;"&gt;ENABLE_EEPROM_EMULATION&lt;/SPAN&gt;,0,0,0);&lt;/P&gt;&lt;P&gt;&amp;nbsp; if((FSTAT!=FSTAT_CCIF_MASK)||(FERSTAT !=0x00))&amp;nbsp; &lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; return EEPROM_INIT_FAIL;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;/P&gt;&lt;P&gt;&amp;nbsp; return EEPROM_INIT_DONE;&lt;/P&gt;&lt;P&gt;}&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&lt;SPAN class="mce_paste_marker"&gt;&lt;/SPAN&gt;&amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 02 Jul 2013 04:24:04 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/MC9S12XEG-EEE-repartitioning-problem/m-p/249106#M9649</guid>
      <dc:creator>adelantesey</dc:creator>
      <dc:date>2013-07-02T04:24:04Z</dc:date>
    </item>
    <item>
      <title>Re: MC9S12XEG EEE repartitioning problem ?</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/MC9S12XEG-EEE-repartitioning-problem/m-p/249107#M9650</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;STRONG&gt;How can I set operating mode of MC9S12XEG128 to special mdoe?&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;As far as I know, In order to repartitioning D-Flash for EEE, I should launch full-Partition-D-Flash command.&lt;/P&gt;&lt;P&gt;Since this command could be launch just in special mode, how can I set operating mode of micro in to special mode.&lt;/P&gt;&lt;P&gt;I’ve connected MODA, MODB &amp;amp; MODC pins to GND and power ON micro in order that micro works in special mode.&lt;/P&gt;&lt;P&gt;But it doesn’t work . after power ON CPU stalled and nothing happened.&lt;/P&gt;&lt;P&gt;For your information, I’m using CyclonePro as programmer.&lt;/P&gt;&lt;P&gt;&lt;SPAN class="mce_paste_marker"&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 02 Jul 2013 09:30:31 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/MC9S12XEG-EEE-repartitioning-problem/m-p/249107#M9650</guid>
      <dc:creator>adelantesey</dc:creator>
      <dc:date>2013-07-02T09:30:31Z</dc:date>
    </item>
    <item>
      <title>Re: MC9S12XEG EEE repartitioning problem ?</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/MC9S12XEG-EEE-repartitioning-problem/m-p/249108#M9651</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Special mode:&lt;/P&gt;&lt;P&gt;MODA and MODB should be connected to GND. MODC is handled by BDM interface (BDM interface holds MODC=BKGD pin tied to GND and reset MCU into special mode).&lt;/P&gt;&lt;P&gt;So, if you debug your program step by step, MCU is already in special mode.&lt;/P&gt;&lt;P&gt;Full Partition D-Flash has FCMD value 0x0F. In case of Full Partition D-Flash command you don’t need take care about erased D-Flash, Full Partition D-Flash command will erase D-Flash and restore partition.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Simplest way for erase all blocks is execution of unsecure command file.&lt;/P&gt;&lt;P&gt;Please connect CyclonePro to board and PC, open debugger window, connect to MCU, go to menu-HC12MultilinkCyclonePro-Unsecure-Enter FCLKDIV value (approximately oscillator clock in MHz – 1, for example 9 for 10MHz crystal).&lt;/P&gt;&lt;P&gt;You MCU should be now completely erased and you can apply Full Partition D-Flash command (only in special mode) or Partition D-Flash command (typically during first run in production).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN class="mce_paste_marker"&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 02 Jul 2013 12:31:08 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/MC9S12XEG-EEE-repartitioning-problem/m-p/249108#M9651</guid>
      <dc:creator>RadekS</dc:creator>
      <dc:date>2013-07-02T12:31:08Z</dc:date>
    </item>
    <item>
      <title>Re: MC9S12XEG EEE repartitioning problem ?</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/MC9S12XEG-EEE-repartitioning-problem/m-p/249109#M9652</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;thanks for your help,&lt;/P&gt;&lt;P&gt;I’ve tried unsecure command in different way, but sometimes it’s not working.&lt;/P&gt;&lt;P&gt;My units has been programmed by cyclonPro in standalone mode.&lt;/P&gt;&lt;P&gt;At the end of programming, units have been secured by cyclonPro with command “SD, SECURE DEVICE”.&lt;/P&gt;&lt;P&gt;Now I want to change partition of D-Flash with reprogramming new code to units again&amp;nbsp; by cyclonPro in standalone mode.&lt;/P&gt;&lt;P&gt;So I ticked check box of “Unsecure target if communication fail” as you can see in the attachement.&lt;/P&gt;&lt;P&gt;After reprogramming by CyclonPro, EEE working properly in some of them but not in all of them (about 10% of units has problem in EEE, their EEE behaves like RAM not EEPROM)&lt;/P&gt;&lt;P&gt;If I reprogram again remaining 10% will be alright.&lt;/P&gt;&lt;P&gt;Conclusion:&lt;/P&gt;&lt;P&gt;Some units should be unsecured 2 or 3 times by cyclonPro in order to be able to repartition by partition-D-Flash command.&lt;/P&gt;&lt;P&gt;Is it normal? Is it a problem of my cyclonPro? Or something else?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 02 Jul 2013 13:06:16 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/MC9S12XEG-EEE-repartitioning-problem/m-p/249109#M9652</guid>
      <dc:creator>adelantesey</dc:creator>
      <dc:date>2013-07-02T13:06:16Z</dc:date>
    </item>
    <item>
      <title>Re: MC9S12XEG EEE repartitioning problem ?</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/MC9S12XEG-EEE-repartitioning-problem/m-p/249110#M9653</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;From your description it looks like some issue with termination of partitioning command.&lt;/P&gt;&lt;P&gt;Has your software implemented watchdog?&lt;/P&gt;&lt;P&gt;Is there any special time for partitioning of MCU in your programming procedure? (I mean programming, disconnecting BDM, reset MCU to normal mode, wait till partitioning is done,… )&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In attachment you can find simple example code for partitioning.&lt;/P&gt;&lt;P&gt;&lt;SPAN class="mce_paste_marker"&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 02 Jul 2013 13:27:40 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/MC9S12XEG-EEE-repartitioning-problem/m-p/249110#M9653</guid>
      <dc:creator>RadekS</dc:creator>
      <dc:date>2013-07-02T13:27:40Z</dc:date>
    </item>
    <item>
      <title>Re: MC9S12XEG EEE repartitioning problem ?</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/MC9S12XEG-EEE-repartitioning-problem/m-p/249111#M9654</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;No, there is no such timing limit nor watchdog enabled.&lt;/P&gt;&lt;P&gt;Watchdog will be enabled after initialization of EEPROM done successfully.&lt;/P&gt;&lt;P&gt;after unit programming finished by cyclonPro, CPU won’t start until power off and on the micro.&lt;/P&gt;&lt;P&gt;It means that micro working in normal mode, not special mode. &lt;/P&gt;&lt;P&gt;I think there is no reason for termination partitioning. &lt;/P&gt;&lt;P&gt;It seems that unsecuring micro by cyclone don’t erase address 0x12_0000&amp;nbsp; through 0x12_0007 sometimes (is it possible?).&lt;/P&gt;&lt;P&gt;Failed units (10% I’ve already discussed) has the correct partition but when application writes to buffer RAM, FERSTAT_ERSVIF0 will be set and data won’t transfer to D-flash.&lt;/P&gt;&lt;P&gt;After reprogramming (again unsecure, program &amp;amp; secure) everything going to be alright.&lt;/P&gt;&lt;P&gt;Confusing !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!&lt;/P&gt;&lt;P&gt;&lt;SPAN class="mce_paste_marker"&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 02 Jul 2013 13:57:33 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/MC9S12XEG-EEE-repartitioning-problem/m-p/249111#M9654</guid>
      <dc:creator>adelantesey</dc:creator>
      <dc:date>2013-07-02T13:57:33Z</dc:date>
    </item>
    <item>
      <title>Re: MC9S12XEG EEE repartitioning problem ?</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/MC9S12XEG-EEE-repartitioning-problem/m-p/249112#M9655</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;You are right. It is confusing.&lt;/P&gt;&lt;P&gt;I don’t think that unsecure command could miss erase same data in flash.&lt;/P&gt;&lt;P&gt;It more looks like issue with clock stability or FCLKDIV value (too short time for erasing/program).&lt;/P&gt;&lt;P&gt;Could you please specify follow points? &lt;/P&gt;&lt;OL style="list-style-type: decimal;"&gt;&lt;LI&gt;Oscillator circuit (part of schematic)&lt;/LI&gt;&lt;LI&gt;XCLKS pin voltage level&lt;/LI&gt;&lt;LI&gt;PLL settings&lt;/LI&gt;&lt;LI&gt;FCLKDIV value&lt;/LI&gt;&lt;/OL&gt;&lt;P&gt;&lt;SPAN class="mce_paste_marker"&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 04 Jul 2013 13:33:34 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/MC9S12XEG-EEE-repartitioning-problem/m-p/249112#M9655</guid>
      <dc:creator>RadekS</dc:creator>
      <dc:date>2013-07-04T13:33:34Z</dc:date>
    </item>
    <item>
      <title>Re: MC9S12XEG EEE repartitioning problem ?</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/MC9S12XEG-EEE-repartitioning-problem/m-p/249113#M9656</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;thanks for your following,&lt;/P&gt;&lt;OL style="list-style-type: decimal;"&gt;&lt;LI&gt;&lt;SPAN style="font-size: 9.0pt; font-family: 'Arial','sans-serif'; color: #333333;"&gt;1. &lt;/SPAN&gt;&lt;SPAN style="font-size: 9.0pt; font-family: 'Arial','sans-serif'; color: #333333;"&gt;Oscillator circuit (part of schematic): Attached file&lt;/SPAN&gt;&lt;/LI&gt;&lt;LI&gt;&lt;SPAN style="font-size: 9.0pt; font-family: 'Arial','sans-serif'; color: #333333;"&gt;2. &lt;/SPAN&gt;&lt;SPAN style="font-size: 9.0pt; font-family: 'Arial','sans-serif'; color: #333333;"&gt;XCLKS pin voltage level : this pin used as a push button (low-side) input. In normal condition is 5.35v but when mentioned input is active it will be 0v as obvious. In initialization this input is not active.&lt;/SPAN&gt;&lt;/LI&gt;&lt;LI&gt;&lt;SPAN style="font-size: 9.0pt; font-family: 'Arial','sans-serif'; color: #333333;"&gt;3. &lt;/SPAN&gt;&lt;SPAN style="font-size: 9.0pt; font-family: 'Arial','sans-serif'; color: #333333;"&gt;PLL settings&lt;/SPAN&gt;&lt;/LI&gt;&lt;/OL&gt;&lt;P style="margin-top: auto; margin-bottom: auto; margin-left: 36pt;"&gt;&lt;SPAN style="font-size: 9.0pt; font-family: 'Arial','sans-serif'; color: #333333;"&gt;&amp;nbsp; &lt;STRONG&gt;static void OSC_Init()&lt;/STRONG&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-top: auto; margin-bottom: auto; margin-left: 36pt;"&gt;&lt;SPAN style="color: #333333; font-size: 9.0pt; font-family: 'Arial','sans-serif';"&gt;&lt;STRONG&gt;{&lt;/STRONG&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-top: auto; margin-bottom: auto; margin-left: 36pt;"&gt;&lt;SPAN style="color: #333333; font-size: 9.0pt; font-family: 'Arial','sans-serif';"&gt;&lt;STRONG&gt;&amp;nbsp;&amp;nbsp; ECLKCTL&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; = 0xC0;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; /* Bit7: NECLK, Bit6: NCLKX2, Bit5: DIV16, Bit4~0: EDIV4~EDIV0&amp;nbsp; */&amp;nbsp;&amp;nbsp; &lt;/STRONG&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-top: auto; margin-bottom: auto; margin-left: 36pt;"&gt;&lt;SPAN style="color: #333333; font-size: 9.0pt; font-family: 'Arial','sans-serif';"&gt;&lt;STRONG&gt;&amp;nbsp;&amp;nbsp; PLLCTL = 0x00;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; /* Bit7: CME, Bit6: PLLON, Bit5: FM1, Bit4: FM0, Bit3: FSTWKP, Bit2: PRE, Bit1: PCE, Bit0: SCME */&lt;/STRONG&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-top: auto; margin-bottom: auto; margin-left: 36pt;"&gt;&lt;SPAN style="color: #333333; font-size: 9.0pt; font-family: 'Arial','sans-serif';"&gt;&lt;STRONG&gt; CLKSEL&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; = 0x00;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; /* Bit7: PLLSEL, Bit6: PSTP, Bit5: XCLKS, Bit4: 0, Bit3: PLLWAI, Bit2: 0, Bit1: RTIWAI, Bit0: COPWAI */&lt;/STRONG&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-top: auto; margin-bottom: auto; margin-left: 36pt;"&gt;&lt;SPAN style="color: #333333; font-size: 9.0pt; font-family: 'Arial','sans-serif';"&gt;&lt;STRONG&gt;&amp;nbsp;&amp;nbsp; /* Fosc =&amp;nbsp; 8MHz&amp;nbsp;&amp;nbsp; */&lt;/STRONG&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-top: auto; margin-bottom: auto; margin-left: 36pt;"&gt;&lt;SPAN style="color: #333333; font-size: 9.0pt; font-family: 'Arial','sans-serif';"&gt;&lt;STRONG&gt;&amp;nbsp;&amp;nbsp; /* Fbus =&amp;nbsp; 16MHz&amp;nbsp; */&amp;nbsp;&amp;nbsp; &lt;/STRONG&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-top: auto; margin-bottom: auto; margin-left: 36pt;"&gt;&lt;SPAN style="color: #333333; font-size: 9.0pt; font-family: 'Arial','sans-serif';"&gt;&lt;STRONG&gt;&amp;nbsp;&amp;nbsp; /* Fbus =&amp;nbsp; Fpll/2 */&lt;/STRONG&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-top: auto; margin-bottom: auto; margin-left: 36pt;"&gt;&lt;SPAN style="color: #333333; font-size: 9.0pt; font-family: 'Arial','sans-serif';"&gt;&lt;STRONG&gt;&amp;nbsp;&amp;nbsp; /* Fpll = (2*Fosc*[SYNDIV+1])/([REFDIV+1][2*POSTDIV]) */&lt;/STRONG&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-top: auto; margin-bottom: auto; margin-left: 36pt;"&gt;&lt;SPAN style="color: #333333; font-size: 9.0pt; font-family: 'Arial','sans-serif';"&gt;&lt;STRONG&gt;&amp;nbsp;&amp;nbsp; SYNR_SYNDIV&amp;nbsp;&amp;nbsp;&amp;nbsp; = 0x01;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; /* Set PLL synthesizer register */&lt;/STRONG&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-top: auto; margin-bottom: auto; margin-left: 36pt;"&gt;&lt;SPAN style="color: #333333; font-size: 9.0pt; font-family: 'Arial','sans-serif';"&gt;&lt;STRONG&gt;&amp;nbsp;&amp;nbsp; SYNR_VCOFRQ&amp;nbsp;&amp;nbsp;&amp;nbsp; = 0x00;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; /* VCO frequency range */ &lt;/STRONG&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-top: auto; margin-bottom: auto; margin-left: 36pt;"&gt;&lt;SPAN style="color: #333333; font-size: 9.0pt; font-family: 'Arial','sans-serif';"&gt;&lt;STRONG&gt;&amp;nbsp;&amp;nbsp; REFDV_REFDV&amp;nbsp;&amp;nbsp;&amp;nbsp; = 0x00;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; /* Set PLL divider register */&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;/STRONG&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-top: auto; margin-bottom: auto; margin-left: 36pt;"&gt;&lt;SPAN style="color: #333333; font-size: 9.0pt; font-family: 'Arial','sans-serif';"&gt;&lt;STRONG&gt;&amp;nbsp;&amp;nbsp; REFDV_REFFRQ&amp;nbsp;&amp;nbsp; = 0x02;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; /* Reference frequency range */&lt;/STRONG&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-top: auto; margin-bottom: auto; margin-left: 36pt;"&gt;&lt;SPAN style="color: #333333; font-size: 9.0pt; font-family: 'Arial','sans-serif';"&gt;&lt;STRONG&gt;&amp;nbsp;&amp;nbsp; POSTDIV&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; = 0x00;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; /* Set CRG postdivider */ &lt;/STRONG&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-top: auto; margin-bottom: auto; margin-left: 36pt;"&gt;&lt;SPAN style="color: #333333; font-size: 9.0pt; font-family: 'Arial','sans-serif';"&gt;&lt;STRONG&gt;&amp;nbsp;&amp;nbsp; PLLCTL = 0x40;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; /* PLL enabled */&amp;nbsp;&amp;nbsp; &lt;/STRONG&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-top: auto; margin-bottom: auto; margin-left: 36pt;"&gt;&lt;SPAN style="color: #333333; font-size: 9.0pt; font-family: 'Arial','sans-serif';"&gt;&lt;STRONG&gt;&amp;nbsp;&amp;nbsp; while(!CRGFLG_LOCK); /* Wait until the PLL is within the desired frequency */ &lt;/STRONG&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-top: auto; margin-bottom: auto; margin-left: 36pt;"&gt;&lt;SPAN style="color: #333333; font-size: 9.0pt; font-family: 'Arial','sans-serif';"&gt;&lt;STRONG&gt;&amp;nbsp;&amp;nbsp; CLKSEL = 0x80;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; /* Bit7: PLLSEL, Bit6: PSTP, Bit5: XCLKS, Bit4: 0, Bit3: PLLWAI, Bit2: 0, Bit1: RTIWAI, Bit0: COPWAI */&amp;nbsp;&amp;nbsp; &lt;/STRONG&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-top: auto; margin-bottom: auto; margin-left: 36pt;"&gt;&lt;SPAN style="color: #333333; font-size: 9.0pt; font-family: 'Arial','sans-serif';"&gt;&lt;STRONG&gt;}&lt;/STRONG&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;OL style="list-style-type: decimal;"&gt;&lt;LI&gt;&lt;SPAN style="font-size: 9.0pt; font-family: 'Arial','sans-serif'; color: #333333;"&gt;4. &lt;/SPAN&gt;&lt;SPAN style="font-size: 9.0pt; font-family: 'Arial','sans-serif'; color: #333333;"&gt;FCLKDIV value : 7&lt;/SPAN&gt;&lt;/LI&gt;&lt;/OL&gt;&lt;P&gt;My current solution for this problem is as follows:&lt;/P&gt;&lt;OL style="list-style-type: decimal;"&gt;&lt;LI&gt;At the beginning of production line, all units are unsecured first by CyclonePro then program new application on it.&lt;/LI&gt;&lt;LI&gt;I’ve added EEPROM test routine to EOL tester.&lt;/LI&gt;&lt;LI&gt;If a unit has been failed, it return to step 1.&lt;/LI&gt;&lt;/OL&gt;&lt;P&gt;Do you think is it a reliable solution? Or any idea?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sat, 06 Jul 2013 05:11:41 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/MC9S12XEG-EEE-repartitioning-problem/m-p/249113#M9656</guid>
      <dc:creator>adelantesey</dc:creator>
      <dc:date>2013-07-06T05:11:41Z</dc:date>
    </item>
    <item>
      <title>Re: MC9S12XEG EEE repartitioning problem ?</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/MC9S12XEG-EEE-repartitioning-problem/m-p/249114#M9657</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;UL&gt;&lt;LI&gt;&lt;SPAN style="font-family: 'Arial', 'sans-serif'; color: #333333; font-size: 9pt;"&gt;2. &lt;/SPAN&gt;&lt;SPAN style="font-family: 'Arial', 'sans-serif'; color: #333333; font-size: 9pt;"&gt;XCLKS pin voltage level : this pin used as a push button (low-side) input. In normal condition is 5.35v but when mentioned input is active it will be 0v as obvious. In initialization this input is not active.&lt;/SPAN&gt;&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;Using XCLKS pin as inpit is tricky. XCLKS defines oscilator mode, Pierce vs loop controlled Pierce. Wiring push button here is quite dangerous. Even if no one presses push button at power up or reset, excess capacitance of push button circuit may make MCU booting with wrong XCLKS mode.&lt;/P&gt;&lt;P&gt;&lt;SPAN class="mce_paste_marker"&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sat, 06 Jul 2013 06:36:16 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/MC9S12XEG-EEE-repartitioning-problem/m-p/249114#M9657</guid>
      <dc:creator>kef</dc:creator>
      <dc:date>2013-07-06T06:36:16Z</dc:date>
    </item>
    <item>
      <title>Re: MC9S12XEG EEE repartitioning problem ?</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/MC9S12XEG-EEE-repartitioning-problem/m-p/249115#M9658</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear Edward &amp;amp; Radek&lt;/P&gt;&lt;P&gt;Thank you very much for your concern.&lt;/P&gt;&lt;P&gt;I’ve tried to simulate error condition. I’ve pushed the button (PE7 = 0) and reset micro by power cycle.&lt;/P&gt;&lt;P&gt;I checked CLKSEL_XCLKS bit. It was zero (&lt;SPAN style="color: red;"&gt;based on my oscillator circuit it should be 1&lt;/SPAN&gt;). But EEPROM &amp;amp; other parts of software worked as expectation and no error observed.&lt;/P&gt;&lt;P&gt;What is your idea?&lt;/P&gt;&lt;P&gt;What is the observable effect of setting micro in wrong XCLKS mode?&lt;/P&gt;&lt;P&gt;&lt;SPAN class="mce_paste_marker"&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 09 Jul 2013 12:40:26 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/MC9S12XEG-EEE-repartitioning-problem/m-p/249115#M9658</guid>
      <dc:creator>adelantesey</dc:creator>
      <dc:date>2013-07-09T12:40:26Z</dc:date>
    </item>
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