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    <title>topic Re: XGATE For SPI in S12 / MagniV Microcontrollers</title>
    <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/XGATE-For-SPI/m-p/220283#M9232</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Yes you can access SPI from XGATE. XGATE can access all peripheral registers, up to 32k of available RAM and up to ~30k of flash. Check the datasheet for details.&lt;/P&gt;&lt;P&gt;Yes, you can send to SPI from XGATE every 19us and much more often.&amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 01 Sep 2010 13:55:58 GMT</pubDate>
    <dc:creator>kef</dc:creator>
    <dc:date>2010-09-01T13:55:58Z</dc:date>
    <item>
      <title>XGATE For SPI</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/XGATE-For-SPI/m-p/220282#M9231</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I need to communicate to a Digital to Analog converter&amp;nbsp;through the SPI Port&amp;nbsp;at a fast rate (1024 times in 20ms = &lt;STRONG&gt;every 19 uS&lt;/STRONG&gt;), with no&amp;nbsp;interruptions.I was thinking of using the XGATE to perform this task (and this task only).&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I'm&amp;nbsp;thinking of&amp;nbsp;using MC9S12XEP100CAL, and my questions are the following::::&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;1. Can I access the SPI ports from the XGATE?&amp;nbsp;&lt;/P&gt;&lt;P&gt;2. All the XGATE needs to do is read from a pre-defined Array of [1024] and write the values at the same rate to the Digital to Analog though SPI. How fast can the XGATE perform this task.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;rlongo&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 01 Sep 2010 04:31:49 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/XGATE-For-SPI/m-p/220282#M9231</guid>
      <dc:creator>rlongo</dc:creator>
      <dc:date>2010-09-01T04:31:49Z</dc:date>
    </item>
    <item>
      <title>Re: XGATE For SPI</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/XGATE-For-SPI/m-p/220283#M9232</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Yes you can access SPI from XGATE. XGATE can access all peripheral registers, up to 32k of available RAM and up to ~30k of flash. Check the datasheet for details.&lt;/P&gt;&lt;P&gt;Yes, you can send to SPI from XGATE every 19us and much more often.&amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 01 Sep 2010 13:55:58 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/XGATE-For-SPI/m-p/220283#M9232</guid>
      <dc:creator>kef</dc:creator>
      <dc:date>2010-09-01T13:55:58Z</dc:date>
    </item>
    <item>
      <title>Re: XGATE For SPI</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/XGATE-For-SPI/m-p/220284#M9233</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;It seems that I am forced to use the Canbus through the XGate? Is this true? Looking at the attachement, I'm not sure if it implies that everything on the right hand side must be connected through the XGATE?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;thanks,&lt;/P&gt;&lt;P&gt;R.Longo&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 26 Nov 2010 05:58:00 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/XGATE-For-SPI/m-p/220284#M9233</guid>
      <dc:creator>rlongo</dc:creator>
      <dc:date>2010-11-26T05:58:00Z</dc:date>
    </item>
    <item>
      <title>Re: XGATE For SPI</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/XGATE-For-SPI/m-p/220285#M9234</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;No, just an misleading diagram. Both the XGATE and the CPU12X can access all the&amp;nbsp;peripherals&amp;nbsp;through the same memory mapped registers.&amp;nbsp;&lt;FONT size="3"&gt;&lt;SPAN style="font-size: 12.1528px; line-height: 14px;"&gt;Interrupts can be routed to either core on a per interrupt basis, in case interrupts are mapped to XGATE, the XGATE handling code can initiate CPU12X interrupts to act as "&lt;/SPAN&gt;&lt;/FONT&gt;&lt;SPAN style="line-height: 24px;"&gt;intelligent&lt;/SPAN&gt;&lt;FONT size="3"&gt;&lt;SPAN style="font-size: 12.1528px; line-height: 14px;"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/FONT&gt;&lt;SPAN style="line-height: 24px;"&gt;peripheral&lt;/SPAN&gt;&lt;FONT size="3"&gt;&lt;SPAN style="font-size: 12.1528px; line-height: 14px;"&gt;".&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/P&gt;&lt;P&gt;The use of the XGATE for any purpose is purely optional.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Daniel&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 26 Nov 2010 07:52:29 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/XGATE-For-SPI/m-p/220285#M9234</guid>
      <dc:creator>CompilerGuru</dc:creator>
      <dc:date>2010-11-26T07:52:29Z</dc:date>
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