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    <title>topic Re: memory map with 9s12dp256 ! in S12 / MagniV Microcontrollers</title>
    <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/memory-map-with-9s12dp256/m-p/215527#M9012</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;RAM on DP256 is mapped at 0x1000 to 0x3FFF out of reset. If you decided to move it to overlap the vector table... then maybe you should stop there and ask youself why you are moving it in the first place.&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 14 Jan 2009 17:36:21 GMT</pubDate>
    <dc:creator>Lundin</dc:creator>
    <dc:date>2009-01-14T17:36:21Z</dc:date>
    <item>
      <title>memory map with 9s12dp256 !</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/memory-map-with-9s12dp256/m-p/215523#M9008</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;&lt;DIV&gt;Hello !&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; i am using mc9s12dp256 microcontroller. my question is: ram space is mapped at address 0xd000 ~ 0xffff, but interrupt vector located at 0xff80 ~ 0xffff, so ram space overlap the interrupt vector. s12FTS256KV2.pdf documents states that "&amp;nbsp;By placing $3F or $3E in the PPAGE register, the bottom respectively top “fixed” 16Kbyte pages can be seen twice in the MCU memory map", does&amp;nbsp;that mean if&amp;nbsp;&amp;nbsp;ram space overlap the interrupt vector, it can also be accessed by place PPAGE register $3F?&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;thanks !&lt;/DIV&gt;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 13 Jan 2009 21:32:26 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/memory-map-with-9s12dp256/m-p/215523#M9008</guid>
      <dc:creator>jeffzxg</dc:creator>
      <dc:date>2009-01-13T21:32:26Z</dc:date>
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    <item>
      <title>Re: memory map with 9s12dp256 !</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/memory-map-with-9s12dp256/m-p/215524#M9009</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;No, PPAGE doesn't apply to RAM and you can't see two copies of RAM&amp;nbsp;in the memory map. PPAGE swithes only flash pages to page window at 8000-BFFF. RAM has priority over flash (over flash page window too)&amp;nbsp;and EEPROM.&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 14 Jan 2009 01:02:13 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/memory-map-with-9s12dp256/m-p/215524#M9009</guid>
      <dc:creator>kef</dc:creator>
      <dc:date>2009-01-14T01:02:13Z</dc:date>
    </item>
    <item>
      <title>Re: memory map with 9s12dp256 !</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/memory-map-with-9s12dp256/m-p/215525#M9010</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;thanks krf.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; but i still not understand.&amp;nbsp; memory space of 9s12 is 64K and address is linear (data and program memory in the same space ) , besides ram has higher prioriy than flash. what does fixed or unpaged memory mean?&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 14 Jan 2009 09:23:13 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/memory-map-with-9s12dp256/m-p/215525#M9010</guid>
      <dc:creator>jeffzxg</dc:creator>
      <dc:date>2009-01-14T09:23:13Z</dc:date>
    </item>
    <item>
      <title>Re: memory map with 9s12dp256 !</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/memory-map-with-9s12dp256/m-p/215526#M9011</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;Fixed means doesn't depend on PPAGE :smileyhappy:. This applies to flash only. There are two fixed flash regions in 64k memory map: 4000h-7fffh and c000h-ffffh.&lt;/DIV&gt;&lt;DIV&gt;Unpaged memory space means memory space directly accessible without any manipulations to paging registers.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;EEPROM, RAM and registers memory block are not paged. If you remap any of these blocks with INITx registers so that they overlap, then EEPROM has priority over flash, RAM over EEPROM and flash, and registers block has highest priority. When memory blocks overlap, then only&amp;nbsp;the highest priority memory block is visible to CPU.&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 14 Jan 2009 16:25:29 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/memory-map-with-9s12dp256/m-p/215526#M9011</guid>
      <dc:creator>kef</dc:creator>
      <dc:date>2009-01-14T16:25:29Z</dc:date>
    </item>
    <item>
      <title>Re: memory map with 9s12dp256 !</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/memory-map-with-9s12dp256/m-p/215527#M9012</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;RAM on DP256 is mapped at 0x1000 to 0x3FFF out of reset. If you decided to move it to overlap the vector table... then maybe you should stop there and ask youself why you are moving it in the first place.&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 14 Jan 2009 17:36:21 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/memory-map-with-9s12dp256/m-p/215527#M9012</guid>
      <dc:creator>Lundin</dc:creator>
      <dc:date>2009-01-14T17:36:21Z</dc:date>
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