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    <title>topic 9s12xd64 ram address in S12 / MagniV Microcontrollers</title>
    <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/9s12xd64-ram-address/m-p/213118#M8922</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;SPAN&gt;I am using 9s12xd64 and 'accidentally' set the ram location start from 0x1000 to 0x1FFF. There are 4K ram on board. It worked fine. I figured out later the ram is supposed to be at the unpaged window of 0x3000. I think if the rpage register is 0xFF, then using the paged window at 0x1000 still makes sense. But I checked the rpage register with Zap debugger. It was 0xfd. Anybody could explain this to me, please. Thanks in advance.&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 02 Sep 2009 02:17:08 GMT</pubDate>
    <dc:creator>D64</dc:creator>
    <dc:date>2009-09-02T02:17:08Z</dc:date>
    <item>
      <title>9s12xd64 ram address</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/9s12xd64-ram-address/m-p/213118#M8922</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;SPAN&gt;I am using 9s12xd64 and 'accidentally' set the ram location start from 0x1000 to 0x1FFF. There are 4K ram on board. It worked fine. I figured out later the ram is supposed to be at the unpaged window of 0x3000. I think if the rpage register is 0xFF, then using the paged window at 0x1000 still makes sense. But I checked the rpage register with Zap debugger. It was 0xfd. Anybody could explain this to me, please. Thanks in advance.&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 02 Sep 2009 02:17:08 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/9s12xd64-ram-address/m-p/213118#M8922</guid>
      <dc:creator>D64</dc:creator>
      <dc:date>2009-09-02T02:17:08Z</dc:date>
    </item>
    <item>
      <title>Re: 9s12xd64 ram address</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/9s12xd64-ram-address/m-p/213119#M8923</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Depending on maskset, you chip may have more RAM and flash than you expect. For example&lt;/P&gt;&lt;P&gt;9S12XD64 0L15Y maskset may have 32kB of RAM. But 9S12XD64 0M84E/1M84E maskset may have 16kB of RAM etc.&lt;/P&gt;&lt;P&gt;I don't know if&amp;nbsp;9S12XD64 's&amp;nbsp;with pure 64k-flash maskset are available already or not, but if you design for 9S12XD64, then you shouldn't use more mamory than is expected in XD64. Else maskset change will break you code.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 02 Sep 2009 13:05:44 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/9s12xd64-ram-address/m-p/213119#M8923</guid>
      <dc:creator>kef</dc:creator>
      <dc:date>2009-09-02T13:05:44Z</dc:date>
    </item>
    <item>
      <title>Re: 9s12xd64 ram address</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/9s12xd64-ram-address/m-p/213120#M8924</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thanks for your response.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;The maskset on my device is 2M42E. Is there any way I could check the detail on the MCU based on maskset?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 02 Sep 2009 18:46:19 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/9s12xd64-ram-address/m-p/213120#M8924</guid>
      <dc:creator>D64</dc:creator>
      <dc:date>2009-09-02T18:46:19Z</dc:date>
    </item>
    <item>
      <title>Re: 9s12xd64 ram address</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/9s12xd64-ram-address/m-p/213121#M8925</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;According to&amp;nbsp;Table 0-1 in the datasheet, Chapter 29 (128k flash module) applies to *M42E maskset... So your S12XD64 is like S12XD128.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 02 Sep 2009 21:08:23 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/9s12xd64-ram-address/m-p/213121#M8925</guid>
      <dc:creator>kef</dc:creator>
      <dc:date>2009-09-02T21:08:23Z</dc:date>
    </item>
    <item>
      <title>Re: 9s12xd64 ram address</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/9s12xd64-ram-address/m-p/213122#M8926</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;I cannot tell if it is s12xd128 or the s12xdg128. But I guess it might be the xdg version since it has 12K RAM.&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 04 Sep 2009 20:56:07 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/9s12xd64-ram-address/m-p/213122#M8926</guid>
      <dc:creator>D64</dc:creator>
      <dc:date>2009-09-04T20:56:07Z</dc:date>
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