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    <title>topic Re: question about SPI on MC9S12d64 in S12 / MagniV Microcontrollers</title>
    <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/question-about-SPI-on-MC9S12d64/m-p/201704#M8147</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thomas,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Yes, multiple SPI slave devices can be connected to a single SPI module configured as a master. You are correct in that you would need a separate slave select or chip select for each slave. Since the SPI module only has a single slave select (SS*) line, you will need to configure the SPI NOT to use the SS pin (i.e. SSOE = 0 in the SPICR1 register). This pin can then be used a GPIO, along with another GPIO pin, as salve select lines for the slave devices.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Gordon&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 26 Sep 2012 14:22:26 GMT</pubDate>
    <dc:creator>GordonD</dc:creator>
    <dc:date>2012-09-26T14:22:26Z</dc:date>
    <item>
      <title>question about SPI on MC9S12d64</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/question-about-SPI-on-MC9S12d64/m-p/201703#M8146</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I am new to freescale and need help for a project at the university. My question is: Can i connect a RTC and a flash memory via SPI to the processor?&lt;BR /&gt;Normaly i would select the peripheral i need per chip select (SS by freescale, right?)? I am usind the "CardS12 modul" if it is important.&lt;BR /&gt;If there are any informations missing, please let me know.&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;thanks and regards,&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thomas&amp;nbsp; &lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 26 Sep 2012 11:35:33 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/question-about-SPI-on-MC9S12d64/m-p/201703#M8146</guid>
      <dc:creator>thommes</dc:creator>
      <dc:date>2012-09-26T11:35:33Z</dc:date>
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    <item>
      <title>Re: question about SPI on MC9S12d64</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/question-about-SPI-on-MC9S12d64/m-p/201704#M8147</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thomas,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Yes, multiple SPI slave devices can be connected to a single SPI module configured as a master. You are correct in that you would need a separate slave select or chip select for each slave. Since the SPI module only has a single slave select (SS*) line, you will need to configure the SPI NOT to use the SS pin (i.e. SSOE = 0 in the SPICR1 register). This pin can then be used a GPIO, along with another GPIO pin, as salve select lines for the slave devices.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Gordon&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 26 Sep 2012 14:22:26 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/question-about-SPI-on-MC9S12d64/m-p/201704#M8147</guid>
      <dc:creator>GordonD</dc:creator>
      <dc:date>2012-09-26T14:22:26Z</dc:date>
    </item>
    <item>
      <title>Re: question about SPI on MC9S12d64</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/question-about-SPI-on-MC9S12d64/m-p/201705#M8148</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hallo Gordon ,&lt;/P&gt;&lt;P&gt;thanks for your fast answer and just to get this right...&lt;/P&gt;&lt;P&gt;I do not use the original SlaveSelect-line but instead two GPIOs which "emulate" two SlaveSelect-lines? &lt;/P&gt;&lt;P&gt;Is there any information in manuals or datasheet which describes this functionality?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thomas&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 27 Sep 2012 09:47:56 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/question-about-SPI-on-MC9S12d64/m-p/201705#M8148</guid>
      <dc:creator>thommes</dc:creator>
      <dc:date>2012-09-27T09:47:56Z</dc:date>
    </item>
    <item>
      <title>Re: question about SPI on MC9S12d64</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/question-about-SPI-on-MC9S12d64/m-p/201706#M8149</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thomas,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Any two GPIO pins can be used as "manual" slave select lines. My point was that when SSOE = 0 in the SPICR1 register, the SPI SS* pin is available as GPIO. As described in the Reference Manual, when&amp;nbsp; SSOE = 1 the SS* pin will be automatically be asserted and de-asserted for each 8-bit transfer. For most slave devices, this is not compatible with the device's command structure. So, the automatic control of SS* is not useful for most slave devices. In fact even with a single slave device on the SPI bus, the SS* line would have to be controlled 'manually' for most slave devices.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Gordon&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 27 Sep 2012 12:58:00 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/question-about-SPI-on-MC9S12d64/m-p/201706#M8149</guid>
      <dc:creator>GordonD</dc:creator>
      <dc:date>2012-09-27T12:58:00Z</dc:date>
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