9S12X SPI handling SPIE, SPTIE

Heppell — Tue, 11 Nov 2008 04:12:12 GMT

I have a question on the proper usage of the SPI Interupts and the SPISR register flags. (SPIF, SPTEF, MODF)

In my current design, I am sending data accross MOSI and then Enabling SPTIE, once the interupt fires I assume data has been sent and Disable SPTIE. I do this for every Transmit. When I want to receive information I need to "clock" it, so I send dummy 8 bytes, and wait for received information which seems to set the SPIF flag and clear it before I read SPISR, or fire the interupt.

Example:
EEPROM Read Operation:
1) Send Read Instruction, Enable SPTIE. (Interupt occurs after TX, disables SPTIE, goes to next operation)
2) Send Address, Enable SPTIE. (Interupt occurs after TX, disables SPTIE, goes to next operation)
3) Send 0x00 to Clock in 8 Bytes of data on Receive (MISO) line.
-> Wait on SPIE interrupt for received data. (Not functioning properly)

*Note CS is active low for the entire operation.

Is there a better way than Disabling/Enabling the interupt, and how can I track the incomming data?

Re: 9S12X SPI handling SPIE, SPTIE

kef — Tue, 11 Nov 2008 13:03:44 GMT

Heppell wrote:
In my current design, I am sending data accross MOSI and then Enabling SPTIE, once the interupt fires I assume data has been sent and Disable SPTIE. I do this for every Transmit.

No. In master mode SPTIE interrupt fires when SPTEF is set. And SPTEF flag gets set not when transfer is complete, but when transmit buffer is ampty. SPTEF just tells you that you can buffer another byte to send. And SPIF is set when transfer is complete.

When I want to receive information I need to "clock" it, so I send dummy 8 bytes, and wait for received information which seems to set the SPIF flag and clear it before I read SPISR, or fire the interupt.

Hm. In master mode I always for transfer complete. And then, after transfer is complete (all 8 bits clocked), I expect new received data available in SPIDR.

You say you clear it (SPIF?) before you read SPISR. To clear SPIF you have to read SPISR, then read SPIDR.

Example:
EEPROM Read Operation:
1) Send Read Instruction, Enable SPTIE. (Interupt occurs after TX, disables SPTIE, goes to next operation)

No, in your case interrupt occurs during "TX", not after. You should enable not SPTIE, but SPIE. When SPIE interrupt fires you can go to 2).

2) Send Address, Enable SPTIE. (Interupt occurs after TX, disables SPTIE, goes to next operation)

SPIE.

topic Re: 9S12X SPI handling SPIE, SPTIE in S12 / MagniV Microcontrollers

9S12X SPI handling SPIE, SPTIE

Re: 9S12X SPI handling SPIE, SPTIE