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    <title>topic Re: XEP100 FCLKDIV - Calculation doesn't match datasheet table in S12 / MagniV Microcontrollers</title>
    <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/XEP100-FCLKDIV-Calculation-doesn-t-match-datasheet-table/m-p/196706#M7811</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear StevieG,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;At the bottom of the table there are two notes:&lt;/P&gt;&lt;P&gt;1. FDIV shown generates an FCLK frequency of &amp;gt;0.8 MHz&lt;/P&gt;&lt;P&gt;2. FDIV shown generates an FCLK frequency of 1.05 MHz&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;that apply to the fmin and fmax values of the table respectively.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;From this it would appear that the flash will tolerate a frequency from 800kHz to 1.05MHz.&amp;nbsp; Using these numbers you can arrive at the fmin and fmax values in the table assuming a formula of&lt;/P&gt;&lt;P&gt;Fflash = Fclk / (fclkdiv+1) with the FURTHER action of of moving the fmin value up so that it does not overlap the next lower fmax value.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;A bit arbitrary I think.&amp;nbsp; Use of a geometric mean as the boundary when they overlap would be more appealing.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Bye&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 30 Apr 2010 12:53:34 GMT</pubDate>
    <dc:creator>pgo</dc:creator>
    <dc:date>2010-04-30T12:53:34Z</dc:date>
    <item>
      <title>XEP100 FCLKDIV - Calculation doesn't match datasheet table</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/XEP100-FCLKDIV-Calculation-doesn-t-match-datasheet-table/m-p/196705#M7810</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I’m using the HCS12XEP100 and need to set the FCLKDIV register. The target frequency is 1MHz (many other flashes require 200K).&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;So the divisor should be pretty simple then, basically it should be whatever the OSC clock is, in MHz.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;There is a table in the XEP reference manual (MC9S12XEP100RMV1.pdf &amp;nbsp;Rev. 1.21 04/2010 page 1151) which shows recommended values for FCLKDIV for OSC values. But the values in the table don’t seem to be simple divisors.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;For example, at an OSC of 10MHz, the recommended value is 0x09, where I might expect a value of 10. I can imagine a (maybe undocumented or did I miss something?) additional +1 in there to get the expected 10.&lt;/P&gt;&lt;P&gt;But the difference is greater at higher OSC frequencies. At an OSC of say 48MHz, the table shows a value of 0x2D, which is 45 where I might expect 48.&amp;nbsp;My imaginary +1 doesn’t work in this case so it seems there is some other factor.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Could you confirm please that the divisor really is a simple divisor with no additional factors,&amp;nbsp;or how the table in the manual was derived? I’m not sure at the moment what FCLKDIV value to use and don’t want to damage the flash. Many thanks.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 29 Apr 2010 16:52:07 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/XEP100-FCLKDIV-Calculation-doesn-t-match-datasheet-table/m-p/196705#M7810</guid>
      <dc:creator>StevieG</dc:creator>
      <dc:date>2010-04-29T16:52:07Z</dc:date>
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    <item>
      <title>Re: XEP100 FCLKDIV - Calculation doesn't match datasheet table</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/XEP100-FCLKDIV-Calculation-doesn-t-match-datasheet-table/m-p/196706#M7811</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear StevieG,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;At the bottom of the table there are two notes:&lt;/P&gt;&lt;P&gt;1. FDIV shown generates an FCLK frequency of &amp;gt;0.8 MHz&lt;/P&gt;&lt;P&gt;2. FDIV shown generates an FCLK frequency of 1.05 MHz&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;that apply to the fmin and fmax values of the table respectively.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;From this it would appear that the flash will tolerate a frequency from 800kHz to 1.05MHz.&amp;nbsp; Using these numbers you can arrive at the fmin and fmax values in the table assuming a formula of&lt;/P&gt;&lt;P&gt;Fflash = Fclk / (fclkdiv+1) with the FURTHER action of of moving the fmin value up so that it does not overlap the next lower fmax value.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;A bit arbitrary I think.&amp;nbsp; Use of a geometric mean as the boundary when they overlap would be more appealing.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Bye&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 30 Apr 2010 12:53:34 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/XEP100-FCLKDIV-Calculation-doesn-t-match-datasheet-table/m-p/196706#M7811</guid>
      <dc:creator>pgo</dc:creator>
      <dc:date>2010-04-30T12:53:34Z</dc:date>
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