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    <title>S12 / MagniV MicrocontrollersのトピックS12XE near RAM size?</title>
    <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/S12XE-near-RAM-size/m-p/196202#M7774</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi all,&lt;/P&gt;&lt;P&gt;in the MC9S12XET512VAL we have 32 Kb RAM.&lt;/P&gt;&lt;P&gt;my question is how much NEAR RAM we have?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I ve searched in docs but I haven't found this information.&lt;/P&gt;&lt;P&gt;in AN3242.pdf I read this but I haven't understood it well:&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P class="MsoNormal"&gt;&lt;SPAN&gt;On the S12XE, there is a new option for alternative mapping of the on-chip RAM into the 4000-7FFF fixed&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="MsoNormal"&gt;&lt;SPAN&gt;memory space as an alternative to page 0xFD of the program flash. This is a write-once configuration that&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="MsoNormal"&gt;&lt;SPAN&gt;allows the RAM to be configured as a 24-Kbytes flat memory map + 4-Kbytes paged (28 Kbytes flat if the&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="MsoNormal"&gt;&lt;SPAN&gt;application does not page the RAM).&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="MsoNormal"&gt;&lt;SPAN&gt;This is enabled by a new RAMHM bit (MMCCTL1, bit 3) and the existing ROMHM bit (MMCCTL1,&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="MsoNormal"&gt;&lt;SPAN&gt;bit 1)&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="MsoNormal"&gt;&lt;SPAN&gt;When both of these bits are set,&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="MsoNormal"&gt;&lt;SPAN&gt;• Accesses to 0x4000–0x7FFF are mapped to 0x0F_C000-0x0F_FFFF in the global memory space&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="MsoNormal"&gt;&lt;SPAN&gt;• Accesses to 0x2000-3FFF are mapped to 0x0F_A000-0x0F_BFFF in the global memory space.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="MsoNormal"&gt;&lt;SPAN&gt;The default value of the RPAGE register remains 0xFD and should be written to 0xF9 in the application&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="MsoNormal"&gt;&lt;SPAN&gt;to configure a 28-Kbyte flat memory map.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="MsoNormal"&gt;&lt;SPAN&gt;Page 0xFD of the flash can be accessed via PPAGE and GPAGE instructions.&lt;/SPAN&gt; &lt;SPAN&gt;By default, RAMHM is&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="MsoNormal"&gt;&lt;SPAN&gt;reserved and the RAM mapping on the S12XE is fully compatible with S12XD.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Any one can help me?&lt;/P&gt;&lt;P&gt;thanks a lot.&lt;/P&gt;&lt;P&gt;Klaud&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 03 Jul 2009 16:02:02 GMT</pubDate>
    <dc:creator>Klaud</dc:creator>
    <dc:date>2009-07-03T16:02:02Z</dc:date>
    <item>
      <title>S12XE near RAM size?</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/S12XE-near-RAM-size/m-p/196202#M7774</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi all,&lt;/P&gt;&lt;P&gt;in the MC9S12XET512VAL we have 32 Kb RAM.&lt;/P&gt;&lt;P&gt;my question is how much NEAR RAM we have?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I ve searched in docs but I haven't found this information.&lt;/P&gt;&lt;P&gt;in AN3242.pdf I read this but I haven't understood it well:&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P class="MsoNormal"&gt;&lt;SPAN&gt;On the S12XE, there is a new option for alternative mapping of the on-chip RAM into the 4000-7FFF fixed&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="MsoNormal"&gt;&lt;SPAN&gt;memory space as an alternative to page 0xFD of the program flash. This is a write-once configuration that&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="MsoNormal"&gt;&lt;SPAN&gt;allows the RAM to be configured as a 24-Kbytes flat memory map + 4-Kbytes paged (28 Kbytes flat if the&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="MsoNormal"&gt;&lt;SPAN&gt;application does not page the RAM).&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="MsoNormal"&gt;&lt;SPAN&gt;This is enabled by a new RAMHM bit (MMCCTL1, bit 3) and the existing ROMHM bit (MMCCTL1,&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="MsoNormal"&gt;&lt;SPAN&gt;bit 1)&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="MsoNormal"&gt;&lt;SPAN&gt;When both of these bits are set,&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="MsoNormal"&gt;&lt;SPAN&gt;• Accesses to 0x4000–0x7FFF are mapped to 0x0F_C000-0x0F_FFFF in the global memory space&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="MsoNormal"&gt;&lt;SPAN&gt;• Accesses to 0x2000-3FFF are mapped to 0x0F_A000-0x0F_BFFF in the global memory space.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="MsoNormal"&gt;&lt;SPAN&gt;The default value of the RPAGE register remains 0xFD and should be written to 0xF9 in the application&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="MsoNormal"&gt;&lt;SPAN&gt;to configure a 28-Kbyte flat memory map.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="MsoNormal"&gt;&lt;SPAN&gt;Page 0xFD of the flash can be accessed via PPAGE and GPAGE instructions.&lt;/SPAN&gt; &lt;SPAN&gt;By default, RAMHM is&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="MsoNormal"&gt;&lt;SPAN&gt;reserved and the RAM mapping on the S12XE is fully compatible with S12XD.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Any one can help me?&lt;/P&gt;&lt;P&gt;thanks a lot.&lt;/P&gt;&lt;P&gt;Klaud&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 03 Jul 2009 16:02:02 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/S12XE-near-RAM-size/m-p/196202#M7774</guid>
      <dc:creator>Klaud</dc:creator>
      <dc:date>2009-07-03T16:02:02Z</dc:date>
    </item>
    <item>
      <title>Re: S12XE near RAM size?</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/S12XE-near-RAM-size/m-p/196203#M7775</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;well,&lt;/P&gt;&lt;P&gt;&amp;nbsp;it is alawys 12 kb = 8 direct RAM + 4 kb paged RAM FD wich used as near RAM...&lt;/P&gt;&lt;P&gt;isn't that?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;thanks,&lt;/P&gt;&lt;P&gt;bye bye&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 10 Jul 2009 15:50:01 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/S12XE-near-RAM-size/m-p/196203#M7775</guid>
      <dc:creator>Klaud</dc:creator>
      <dc:date>2009-07-10T15:50:01Z</dc:date>
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