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    <title>S12 / MagniV MicrocontrollersのトピックRe: Accessing paged RAM from XGATE - S12XEQ384</title>
    <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/Accessing-paged-RAM-from-XGATE-S12XEQ384/m-p/195883#M7755</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Have you confirmed that your code is getting copied to the right region of memory?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Do the XGATE interrupt vectors point to the right address?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;James&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 24 Jul 2009 20:22:12 GMT</pubDate>
    <dc:creator>jsmcortina</dc:creator>
    <dc:date>2009-07-24T20:22:12Z</dc:date>
    <item>
      <title>Accessing paged RAM from XGATE - S12XEQ384</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/Accessing-paged-RAM-from-XGATE-S12XEQ384/m-p/195881#M7753</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;i am using a S12XEQ384 with 24 kB RAM. I initially linked XGATE data to unpaged RAM. Later due to certain reasons i need to move it to paged RAM. Since then the cpu application code never runs and always an XGATE access violation occurs.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;here is a section of my prm file:&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; //RAM_XGATE_STK = READ_WRITE&amp;nbsp; 0xFA1000 TO 0xFA10FF ALIGN 2 [1:1]; /* The stack is set by the XGATE compiler option -Cstv=A100 */&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; RAM_XGATE_DATA= READ_WRITE&amp;nbsp; 0xFA1100 TO 0xFA12FF ALIGN 2 [1:1]; /* word align for XGATE accesses */&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; RAM_FA&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; = READ_WRITE&amp;nbsp; 0xFA1300 TO 0xFA1FFF; // ALIGN 2[1:1]; /* is also mapped to XGATE:&amp;nbsp; 0xA000..0xAFFF */&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; RAM_FB&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; = READ_WRITE&amp;nbsp; 0xFB1000 TO 0xFB1FFF;&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; RAM_FC&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; = READ_WRITE&amp;nbsp; 0xFC1000 TO 0xFC1FFF;&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; RAM_FD&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; = READ_WRITE&amp;nbsp; 0xFD1000 TO 0xFD1FFF;&lt;BR /&gt;/*&amp;nbsp;&amp;nbsp;&amp;nbsp; RAM_FE&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; = READ_WRITE&amp;nbsp; 0xFE1000 TO 0xFE1FFF; intentionally not defined: equivalent to RAM: 0x2000..0x2FFF */&lt;BR /&gt;/*&amp;nbsp;&amp;nbsp;&amp;nbsp; RAM_FF&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; = READ_WRITE&amp;nbsp; 0xFF1000 TO 0xFF1FFF; intentionally not defined: equivalent to RAM: 0x3000..0x3FFF */&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Can someone help on this ?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;Saravana&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Added p/n to subject.&lt;/P&gt;&lt;DIV class="message-edit-history"&gt;&lt;SPAN class="edit-author"&gt;Message Edited by NLFSJ on&lt;/SPAN&gt; &lt;SPAN class="local-date"&gt;2009-07-02&lt;/SPAN&gt; &lt;SPAN class="local-time"&gt;12:57 PM&lt;/SPAN&gt;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 02 Jul 2009 22:58:32 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/Accessing-paged-RAM-from-XGATE-S12XEQ384/m-p/195881#M7753</guid>
      <dc:creator>saravanakumar_m</dc:creator>
      <dc:date>2009-07-02T22:58:32Z</dc:date>
    </item>
    <item>
      <title>Re: Accessing paged RAM from XGATE - S12XEQ384</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/Accessing-paged-RAM-from-XGATE-S12XEQ384/m-p/195882#M7754</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;The main different in between paged and unpaged is for the S12, is the data shared in between the cores?&lt;/P&gt;&lt;P&gt;Also how does it fail, does any code get executed for the XGATE at all?&lt;/P&gt;&lt;P&gt;How is the code for the XGATE mapped, flash?&lt;/P&gt;&lt;P&gt;Is the XGATE stack properly initialized?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I did not notice anything special from the provided information, I would think we need more hints on what is going on. With a bdm it should not be too hard to see what fails.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Daniel&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 03 Jul 2009 06:56:17 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/Accessing-paged-RAM-from-XGATE-S12XEQ384/m-p/195882#M7754</guid>
      <dc:creator>CompilerGuru</dc:creator>
      <dc:date>2009-07-03T06:56:17Z</dc:date>
    </item>
    <item>
      <title>Re: Accessing paged RAM from XGATE - S12XEQ384</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/Accessing-paged-RAM-from-XGATE-S12XEQ384/m-p/195883#M7755</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Have you confirmed that your code is getting copied to the right region of memory?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Do the XGATE interrupt vectors point to the right address?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;James&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 24 Jul 2009 20:22:12 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/Accessing-paged-RAM-from-XGATE-S12XEQ384/m-p/195883#M7755</guid>
      <dc:creator>jsmcortina</dc:creator>
      <dc:date>2009-07-24T20:22:12Z</dc:date>
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