<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: Timer malfunction 9S12DP512 in S12 / MagniV Microcontrollers</title>
    <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/Timer-malfunction-9S12DP512/m-p/193756#M7654</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;When fast flag clear is set you can't clear timer flags and modulus down counter flag writing ones&amp;nbsp;to flag bits. I guess this is your case. It's not eenough to clear timer flags reading capture registers you also need to read MCCNT to clear MCZF.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 28 Mar 2011 12:00:29 GMT</pubDate>
    <dc:creator>kef</dc:creator>
    <dc:date>2011-03-28T12:00:29Z</dc:date>
    <item>
      <title>Timer malfunction 9S12DP512</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/Timer-malfunction-9S12DP512/m-p/193755#M7653</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;My application also uses the Modulus system which generates an interrupt when downcounter reaches zero. The counter automatically reloads. This may or may not be related to the following problem.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;The ECT_16B8C Block User Guide V01.02 states "When TFFCA bit in TSCR register is set, a read from an input capture channel ($10-$1F) will cause the corresponding channel flag CnF to be cleared".&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;The Timer oscillator in this application freeruns and is used for input capture interrupts.&amp;nbsp; If the TFFCA bit in TSCR1 is set to provide fast interrupt flag clearing on input capture, then the micro will hang up. A better solution, but which takes more time, is to clear the TFLG1 interrupt flag in the interrupt service routine.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Does anyone know if this is a defect in the chip?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 28 Mar 2011 07:11:55 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/Timer-malfunction-9S12DP512/m-p/193755#M7653</guid>
      <dc:creator>astro_goto</dc:creator>
      <dc:date>2011-03-28T07:11:55Z</dc:date>
    </item>
    <item>
      <title>Re: Timer malfunction 9S12DP512</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/Timer-malfunction-9S12DP512/m-p/193756#M7654</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;When fast flag clear is set you can't clear timer flags and modulus down counter flag writing ones&amp;nbsp;to flag bits. I guess this is your case. It's not eenough to clear timer flags reading capture registers you also need to read MCCNT to clear MCZF.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 28 Mar 2011 12:00:29 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/Timer-malfunction-9S12DP512/m-p/193756#M7654</guid>
      <dc:creator>kef</dc:creator>
      <dc:date>2011-03-28T12:00:29Z</dc:date>
    </item>
  </channel>
</rss>

