topic Re: 9S12DP512 PLL operation in S12 / MagniV Microcontrollers

9S12DP512 PLL operation

astro_goto — Mon, 19 Apr 2010 22:30:34 GMT

Crystal freq is 16 MHz with clock freq 8MHz. I want to boost clock freq to 24 MHz with PLL. Are there any APP notes showing how to do this? My application is a computer driven telescope written in assembly language and faster clock speed is needed for all the calculations involved.

Thanx,

astro_goto

Re: 9S12DP512 PLL operation

astro_goto — Wed, 21 Apr 2010 20:55:12 GMT

I found my own solution: PLL operation is not as difficult as I had imagined.

The basic calculation isgiven in the Clocks and Generator (CRG) User Guide:

PLLCLK = 2 x OSCCLK x [SYNR + 1] / [REFDV + 1]

where:

OSCCLK is the crystal frequency: 16MHz in my case which generates a 8MHz bus clock (too slow)

PLLCLK will be 48MHz to generate a 24MHz bus clock instead of 8MHz

Only 5 lines of assembly code are needed to implement the PLL:

movb #2,SYNR ;PLLCLK = 2 * OSCCLK * (SYNR+1)/(REFDV+1)

movb   #1,REFDV   ;PLLCLK = 2 * 16MHz * (2 + 1)/(1 + 1) = 48MHz
    bset   PLLCTL,#$60   ;PLLON=1, AUTO=1
    brclr   CRGFLG,LOCK,*   ;wait here until PLL is stable and LOCK is set
   bset   CLKSEL,#$80      ;now select PLLCLK/2 as bus clock (e-clock)

For the MC9S12DP512 chip the following definitions apply:

SYNR: equ $0034 ; $ implies hexadecimal number

REFDV: equ $0035

CLKSEL: equ $0039

PLLCTL: equ $003A

CRGFLG: equ $0037

LOCK: equ $08

I hope this is helpful to someone.

astro_goto

Re: 9S12DP512 PLL operation

MJW — Wed, 21 Apr 2010 21:16:57 GMT

Don't forget the filter components on the XFC pin, if you use the PLL on a 0.25 um S12 device.

There is a utility available to help with component selection for the filter (to find it type "HCS12PLL" in the "Enter Keyword" search field)

Hope that helps.

MJW