S12 / MagniV MicrocontrollersのトピックRe: SPI interfacing

SPI interfacing

tormentor — Thu, 22 Dec 2011 20:29:02 GMT

hey there. am working on SPI interface between two microcontrollers. mc9s12xdt512. help me out with the code.

#include /* common defines and macros */

#include /* derivative information */

#pragma LINK_INFO DERIVATIVE "mc9s12xdt512"

#include "main_asm.h" /* interface to the assembly module */

void main(void)

{

unsigned char x;

SPI0BR=0x20;

SPI0CR1=0x54;

SPI0CR2=0x0;
WOMS=0x0;

for(; {

while(!(SPI0SR & SPI0SR_SPTEF_MASK));

SPI0DR='B';

while(!(SPI0SR & SPI0SR_SPIF_MASK))

x=SPI0DR;

}

thisis my code for transmitting a character. when i run it on a full chip simulation mode, i can see the character 'B' at SPI0DR. but when i run it on the controllers, i dannot see any thing at SPI0DR. on the recieveing side my code is

void main(void)

{

unsigned char x;

SPI0BR=0x20;

SPI0CR1=0x44;

SPI0CR2=0x0;

WOMS=0x0;

for(; {

while(!(SPI0SR & SPI0SR_SPTEF_MASK));

SPI0DR=0;

while(!(SPI0SR & SPI0SR_SPIF_MASK))

x=SPI0DR;

} } my status register reads 20. and nothing at SPI0DR. help me out

Re: SPI interfacing

PLacerenza — Sat, 21 Jan 2012 05:00:38 GMT

If you look at the user's guide for the mc9s12xdt512, each SPI port can be set to one of two sets of 4 pins, which is taken care of by MODRR (Module Routing Register). Make sure that both of your SPI ports are set to the correct bank of 4 pins by setting or clearing the correct bit of MODRR.

I had a similar issue, although I was only receiving, I wasn't seeing SCLK pulses on an oscilloscope when I knew I was transmitting, and had a tough time finding out which bank 0 sent it to, and which 1 sent it to.

Look up the PIM's block user's guide (Port Integration Module) and look up MODRR for your port and check if it's set for your bank of pins.

I'd love if Freescale took care there being no obvious correlation between the two in the user's guide(s) unless you really pour over them for a while. Everything else is fairly well documented.

Re: SPI interfacing

bigmac — Sat, 21 Jan 2012 12:59:58 GMT

Hello, and welcome to the forum.

Firstly, to clarify some terminology -

The SPI module may be configured as either a master, or a slave. Both configurations are capable of handling data flow in both directions simultaneously. For the master, data is sent via MOSI, and received via MISO. For the slave end, the roles are reversed. The master end always initiates each data transfer, and generates the clock pulses required.

The code snippet that you have shown is suitable for the SPI master, where a send byte is initiated, and the received value is available once the SPIF flag becomes set.

For the SPI slave, the operation is quite different. Any data to be returned to the master on the next transfer needs to be loaded to the buffer prior to SS becoming active. Following the receipt of data from the master (and the return of the data already within the buffer), the SPIF flag will become set. If data is to be returned in response, this will commence on the next transfer. This may require that the master allow adequate time for the slave to process the data, before initiating the transfer (usually with "dummy" send bytes). Alternatively, the slave might signal back to the master when it is ready, or requires some attention, using an extra GPIO line.

To minimize the delay within the master, SPI interrupts are freqently used for the SPI slave. If the response requires a sequence of more than one byte, the double bufferering capability of the SPI module can be put to use. A second byte can be loaded to the buffer, prior to the first byte being returned.

For communications between two MCUs, it is also possible for each MCU to default to slave mode, and only become a master when it requires to initiate an action (a multi-master situation). But this method requires more complex code to handle potential conflicts.

Regards,

Mac