topic S12X clear interrupt in S12 / MagniV Microcontrollers

S12X clear interrupt

Drea — Tue, 19 Feb 2008 17:58:54 GMT

Hi,

I have a little problem. Our system based on two different processors. They are connected over CAN.

When my processor (S12XDP512) gets a special telegram it have to change its state. It means that it gets an rx-interrupt and into this interrupt it calls a function. So it doesn't return the ISR. My problem is, that all interrupts are disabled. I called cli but it doesn't work. My emu shows the register and there is a register ccr. I detect that I have to clear the high byte and than the interrupts still works. But I don't know where I can find this register in my processor. I would like to "kill" the old interrupt.

I hope, somebody can help me

Re: S12X clear interrupt

JimDon — Tue, 19 Feb 2008 22:16:36 GMT

CLI reenables the interrupt.

However, you usually can't just decide to not return from an interrupt.
For one thing, there are items pushed on the stack.
For another, the code was running may need to finish. There is no way to predict what code you interrupted.
An don't for get to clear the in the pending interrupt, if you have not done so.

Sounds like a hack you may later regert.

Re: S12X clear interrupt

allawtterb — Tue, 19 Feb 2008 22:45:58 GMT

You might want to re-examine if you really need this quick of a response time. Perhaps you are spending too much time in the ISR that you need to interrupt if this is the case. Is there any extra information that you can provide? How long is this ISR? Is this fast of reponse truly needed?

Re: S12X clear interrupt

kef — Wed, 20 Feb 2008 00:32:16 GMT

In S12X, just CLI inside ISR (interrupt nesting) is not enough to reenable interrupts. By default all S12X interrupt priority levels are set to 1. Normally, in order to allow interrupt nesting, interrupt controller setup procedure adjusts interrupt priorities. Then interrupt service routine just CLI s to allow higher priority interrupts. Another option is like Drea noticed, would be to clear CCR IPL bits and CLI.