topic Re: PCB design using S12XEP100CAL in S12 / MagniV Microcontrollers

PCB design using S12XEP100CAL

Pascalfm — Sat, 10 Apr 2010 08:13:27 GMT

I've design a 3 layer PCB using a S12XEP100CAL as the main controller. I've only solder the S12X with the filter capacitors and crystal to check if everything was working properly but the controller didn't response to my P&E multilink.

I've check all the connection on an empty board and there is no shortcut between any output of the voltage regulator also all ground ar good (reading .10 ohm between each other). I've measure the output of the voltage regulator and I've got the following voltage:

vdd: 0.58v

Vddf: 0.58v

vddpll: 4.2v

I've follow the pcb guideline in the datasheet for the board layout and I've check the schematic to be sure that every pins was connect as indicated on the datasheet. I must be missing something obvious but it's my first design using an S12X.

Re: PCB design using S12XEP100CAL

DPB — Mon, 12 Apr 2010 20:19:38 GMT

Hello

It is not normally possible for the S12XEP100 to generate 4.2V at the VDDPLL pin.

The presence of 4.2V at the VDDPLL pin indicates either device internal damage or a PCB shortcircuit.

Can you isolate the VDDPLL pin from the rest of the board (for example by bending the pin) and measure VDDPLL on the pin on then on the board, to determine the source?

What voltage is applied to VDDR, VDDX and VDDA?

Could the low VDD and VDDF voltages be caused by an incorrect polarity of a tantalum capacitor causing damage to it?

In the schematic attachment the VSSA1 connection seems to be floating but I guess this was just shifted when drawing the power routing diagram.

DPB

Re: PCB design using S12XEP100CAL

Pascalfm — Thu, 15 Apr 2010 02:39:52 GMT

i've bend the pin and I got 4.2V on the VDDPLL pin and 0V on the board.

5.0V is applied on VVDR, VDDX, VDDA

The polarity of the tantalum capacitor is correct. I've also test with ceramic capacitor just to be sure.

For the VSSA1 it's just a shif in the drawing that I didn't take the time to correct but it's connect properly.

I've the board with 3 different chip (from 2 different bath) and always get the same result so i'm guessing there's something wrong with the board that i didn't find yet

Re: PCB design using S12XEP100CAL

DPB — Thu, 15 Apr 2010 15:39:00 GMT

Hello

So the 4.2V on VDDPLL is apparently being generated by the device, which is not normal because this operates in the 1.8V range, supplied by the internal regulator. There are however paths from the XTAL and EXTAL pins through ESD protection

devices that could generate voltages in this range if 5V were applied to XTAL or EXTAL.

You could check the XTAL and EXTAL connections, to ensure no short to 5V.

DPB

Re: PCB design using S12XEP100CAL

Pascalfm — Thu, 22 Apr 2010 03:45:10 GMT

There is no short between XTAL or EXTAL and the board.

I've bend both pin and I read 4.2V on XTAL... Do I need to put some kind of voltage divider before or after the crystal to be sure to get a tension below 1.8V on the XTAL pin?

Re: PCB design using S12XEP100CAL

kef — Thu, 22 Apr 2010 13:07:30 GMT

It's obvious, but did you check if pin#1 key on MCU case matches pin#1 pad on PCB?

Re: PCB design using S12XEP100CAL

Pascalfm — Sat, 24 Apr 2010 00:28:52 GMT

Yes the pin#1 matches the pad on the pcb. I've put some resistor and now I get about 0.5 volt on XTAL and EXTAL but still get the same result on VDDPLL, I've tried with another MCU in case I haved burn the MCU with my previous test but still the same..

Re: PCB design using S12XEP100CAL

Pascalfm — Thu, 29 Apr 2010 08:37:39 GMT

I've manage to get all the voltage right and I checked the oscillator and I get 16 Mhz but when I connect to the target.

I use a P&E multilink. When I use autodetect speed, I can see the program running the script to find the right speed. When I try to enter manually the io_delay_cnt it still can't connect. When I calcul the io_delay_cnt with the formula "IO_DELAY_CNT = (120000000 / Fbus) – 1" I get 1.4 but if I enter either 1 or 2 it doesn't work... any idea? I didn't get a scope so I coudn't probe the BDM and RESET pin but I'll try to do it soon.

Re: PCB design using S12XEP100CAL

kef — Thu, 29 Apr 2010 10:40:27 GMT

Without PLL Fbus is oscilator clock / 2. Delay counter is 120MHz/8MHz - 1 = 14