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    <title>S12 / MagniV MicrocontrollersのトピックRe: [MC9S12C64] Interrupt Priority for Input Capture</title>
    <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/MC9S12C64-Interrupt-Priority-for-Input-Capture/m-p/188961#M7255</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;How does clear flag code looks like? C? Asm?&lt;/P&gt;&lt;P&gt;Input capture misses events only when input pulse is too narrow (&amp;lt;2&amp;nbsp;bus clocks as stated in datasheets).&lt;/P&gt;&lt;P&gt;Another problem maybe&amp;nbsp;that new capture event overwrites old TCx, so you need to service IC on time (ECT timer has some extra capture features like buffered capture etc).&lt;/P&gt;&lt;P&gt;HPRIO won't help a lot. It is effective only when two or more interrupts ar pending at the same time. It matters when you expect two or more interrupts happening at exactly the same time, and you wish to service one of them first.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 09 Dec 2011 04:09:01 GMT</pubDate>
    <dc:creator>kef</dc:creator>
    <dc:date>2011-12-09T04:09:01Z</dc:date>
    <item>
      <title>[MC9S12C64] Interrupt Priority for Input Capture</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/MC9S12C64-Interrupt-Priority-for-Input-Capture/m-p/188960#M7254</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi All,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I've two IOC pin IOC0 and IOC3 and use them to capture input signal's pulse width. The frequency of IOC0's signal is greater than IOC3's. But sometimes the IOC3 pin will lost to capture some signals. If I want to guarantee that the signal to IOC3 pin will not lost to capture signal. How can I do?&lt;/P&gt;&lt;P&gt;Changing the priority of interrupt for IOC3 as highest. (HPRIO = 0xE8) ? Or you have another solution, please tell me. Thanks a lot.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Reagrds,&lt;/P&gt;&lt;P&gt;Pogo&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 08 Dec 2011 23:30:54 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/MC9S12C64-Interrupt-Priority-for-Input-Capture/m-p/188960#M7254</guid>
      <dc:creator>Pogo</dc:creator>
      <dc:date>2011-12-08T23:30:54Z</dc:date>
    </item>
    <item>
      <title>Re: [MC9S12C64] Interrupt Priority for Input Capture</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/MC9S12C64-Interrupt-Priority-for-Input-Capture/m-p/188961#M7255</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;How does clear flag code looks like? C? Asm?&lt;/P&gt;&lt;P&gt;Input capture misses events only when input pulse is too narrow (&amp;lt;2&amp;nbsp;bus clocks as stated in datasheets).&lt;/P&gt;&lt;P&gt;Another problem maybe&amp;nbsp;that new capture event overwrites old TCx, so you need to service IC on time (ECT timer has some extra capture features like buffered capture etc).&lt;/P&gt;&lt;P&gt;HPRIO won't help a lot. It is effective only when two or more interrupts ar pending at the same time. It matters when you expect two or more interrupts happening at exactly the same time, and you wish to service one of them first.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 09 Dec 2011 04:09:01 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/MC9S12C64-Interrupt-Priority-for-Input-Capture/m-p/188961#M7255</guid>
      <dc:creator>kef</dc:creator>
      <dc:date>2011-12-09T04:09:01Z</dc:date>
    </item>
    <item>
      <title>Re: [MC9S12C64] Interrupt Priority for Input Capture</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/MC9S12C64-Interrupt-Priority-for-Input-Capture/m-p/188962#M7256</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;PRE&gt;interrupt void ISR_Timer0(void){    ...  //local variable define    TFLG1 |= 0x01; //Clear flag    ...  // do some calculation}interrupt void ISR_Timer3(void){    ...  //local variable define    TFLG1 |= 0x08; //Clear flag    ...  //do some calculation}&lt;/PRE&gt;&lt;P&gt;&amp;nbsp;Now, the ISR_Timer3 will lost some signal interrupt. &amp;nbsp;If I clear flag after doing some calculation, can I solve this problem?&lt;/P&gt;&lt;P&gt;Thanks for your reply!!&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Pogo&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 29 Oct 2020 09:40:11 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/MC9S12C64-Interrupt-Priority-for-Input-Capture/m-p/188962#M7256</guid>
      <dc:creator>Pogo</dc:creator>
      <dc:date>2020-10-29T09:40:11Z</dc:date>
    </item>
    <item>
      <title>Re: [MC9S12C64] Interrupt Priority for Input Capture</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/MC9S12C64-Interrupt-Priority-for-Input-Capture/m-p/188963#M7257</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;So I was right suspecting that you are clearing timer flags incorrectly.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;FONT color="#ff0000"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; TFLG1 |= 0x01; //Clear flag&lt;/FONT&gt;&lt;BR /&gt;&amp;nbsp;^^ here you are clearing all TFLG1 flags, including channel 0 and 3 flags&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;FONT color="#ff0000"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; TFLG1 |= 0x08; //Clear flag&lt;/FONT&gt;&lt;BR /&gt;Same &amp;nbsp;^^ here. You are clearing all TFLG1 flags, including channel 0 and 3 flags&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Search forum for flag clearing like stuf and you will find it desribed many times. Reading TFLG1, ORing read bit pattern with&amp;nbsp; mask of flag&amp;nbsp; you are interested in, then writing resulting bitpattern back to TFLG1, you are writing "1" not just to flag you are interested in, but you write more "1"-es and clearing not just flag you are interested in. Correct code to clear channel&amp;nbsp;3 flag is either&lt;/P&gt;&lt;P&gt;&lt;FONT color="#008000"&gt;&amp;nbsp;&lt;/FONT&gt;&lt;/P&gt;&lt;P&gt;&lt;FONT color="#339966"&gt;&amp;nbsp;&amp;nbsp; TFLG1 = (1&amp;lt;&amp;lt;3);&lt;/FONT&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;or&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;FONT color="#339966"&gt;&amp;nbsp; TFLG1 &amp;amp;= (1&amp;lt;&amp;lt;3); // please note that there's no ~&amp;nbsp;operator in front of bitpattern on the right&lt;/FONT&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 09 Dec 2011 13:07:16 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/MC9S12C64-Interrupt-Priority-for-Input-Capture/m-p/188963#M7257</guid>
      <dc:creator>kef</dc:creator>
      <dc:date>2011-12-09T13:07:16Z</dc:date>
    </item>
    <item>
      <title>Re: [MC9S12C64] Interrupt Priority for Input Capture</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/MC9S12C64-Interrupt-Priority-for-Input-Capture/m-p/188964#M7258</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Always, I repeat, always disassemble ISRs where you clear interrupt source flags. Incorrectly cleared interrupt flags is possibly the greatest cause of bugs in embedded systems, no matter what MCU flavour you are using. You have to read the disassembly and see what actually goes on, and whether this is compatible with the hardware registers or not.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;For this particular case, Kef is likely assuming that you are using the Codewarrior, where the cod&lt;FONT&gt;e TFLG |= 0x01 is indeed incorrect. CW will translate that to a read-modify-write access, and since TFLG is cleared by writing 1 to a flag, all flags will be cleared and not just the one you were interested in. But on another compiler, the same code could give the correct output, using a single bit set instruction instead.&lt;BR /&gt;&lt;/FONT&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 09 Dec 2011 20:58:03 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/MC9S12C64-Interrupt-Priority-for-Input-Capture/m-p/188964#M7258</guid>
      <dc:creator>Lundin</dc:creator>
      <dc:date>2011-12-09T20:58:03Z</dc:date>
    </item>
    <item>
      <title>Re: [MC9S12C64] Interrupt Priority for Input Capture</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/MC9S12C64-Interrupt-Priority-for-Input-Capture/m-p/188965#M7259</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Lundin, pelase stop spreading rumors about read modify write instructions. You are wrong! First of all I didn't say that TFLG1 |= 0x1 is correct. Second, IT DOESN'T MATTER&amp;nbsp;WHAT COMPILER you will use, and if that compiler will use BSET or LDAA/ORAA/STAA like sequence, in all imagineable cases it won't work properly and will clear all flags that are set in this flags register! The same applies to bitfields provided by Freescale compilers. TFLG1_C0F = 1 will clear all TFLG1 flags. TFLG1_C0F = 0 will clear all TFLG1 flags except C0F.&lt;/P&gt;&lt;P&gt;INDEED READ MODIFY WRITE instructions&amp;nbsp;are ABSULUTELY OK, provided you are using&amp;nbsp;them properly. What's wrong with these codes to clear bit 3 in TFLG1? These&amp;nbsp;work perfectly well:&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; TFLG1 &amp;amp;= (1&amp;lt;&amp;lt;3); // please note that there's no ~ on the righ like would be used to clear bits in regular variables.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;and&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp; BCLR&amp;nbsp; TFLG1, #~(1&amp;lt;&amp;lt;3)&amp;nbsp;&amp;nbsp; or&amp;nbsp;equivalent &amp;nbsp;&amp;nbsp;BCLR TFLG1, #0xF7&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 09 Dec 2011 23:51:57 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/MC9S12C64-Interrupt-Priority-for-Input-Capture/m-p/188965#M7259</guid>
      <dc:creator>kef</dc:creator>
      <dc:date>2011-12-09T23:51:57Z</dc:date>
    </item>
    <item>
      <title>Re: [MC9S12C64] Interrupt Priority for Input Capture</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/MC9S12C64-Interrupt-Priority-for-Input-Capture/m-p/188966#M7260</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi kef,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks for your reply.&lt;/P&gt;&lt;P&gt;I've serach all "clear flag" keyword in this forum.&lt;/P&gt;&lt;P&gt;If I want to clear Timer0 and Timer3, I need to write the belowing code to clear them.&lt;/P&gt;&lt;P&gt;TFLG1 &amp;nbsp;= 0x01; //Clear Timer 0 flag&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;TFLG1 = 0x08; //Clear Timer 3 flag.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Pogo&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 12 Dec 2011 16:38:44 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/MC9S12C64-Interrupt-Priority-for-Input-Capture/m-p/188966#M7260</guid>
      <dc:creator>Pogo</dc:creator>
      <dc:date>2011-12-12T16:38:44Z</dc:date>
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