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    <title>topic Internal cache for S12X in S12 / MagniV Microcontrollers</title>
    <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/Internal-cache-for-S12X/m-p/174352#M6034</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;Hi,&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;I intend to clear internal cache (instruction queue, data queue) for S12X. Please suggest if this is possible and how.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Thanks.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Regards,&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;Ajay&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 19 Dec 2007 16:43:46 GMT</pubDate>
    <dc:creator>JadhavAj</dc:creator>
    <dc:date>2007-12-19T16:43:46Z</dc:date>
    <item>
      <title>Internal cache for S12X</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/Internal-cache-for-S12X/m-p/174352#M6034</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;Hi,&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;I intend to clear internal cache (instruction queue, data queue) for S12X. Please suggest if this is possible and how.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Thanks.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Regards,&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;Ajay&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 19 Dec 2007 16:43:46 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/Internal-cache-for-S12X/m-p/174352#M6034</guid>
      <dc:creator>JadhavAj</dc:creator>
      <dc:date>2007-12-19T16:43:46Z</dc:date>
    </item>
    <item>
      <title>Re: Internal cache for S12X</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/Internal-cache-for-S12X/m-p/174353#M6035</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;There's no data queue / cache in S12X.&lt;/DIV&gt;&lt;DIV&gt;There's only a instruction queue. Just branch/jump somewhere and queue will be "emptied and reloaded".&amp;nbsp;Why do you want to clear instruction queue, are you doing something very&amp;nbsp;smart?&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 19 Dec 2007 17:13:17 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/Internal-cache-for-S12X/m-p/174353#M6035</guid>
      <dc:creator>kef</dc:creator>
      <dc:date>2007-12-19T17:13:17Z</dc:date>
    </item>
    <item>
      <title>Re: Internal cache for S12X</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/Internal-cache-for-S12X/m-p/174354#M6036</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;I am writing RAMTest algorithm. One of the requirement is to clear the internal cache after writing to RAM and before reading back from RAM.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Do you mean if I&amp;nbsp;make some branch/jump instruction, internal cache(instruction queue)&amp;nbsp;will &amp;nbsp;get cleared. Will this have some side-effect on existing code?&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 19 Dec 2007 20:20:07 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/Internal-cache-for-S12X/m-p/174354#M6036</guid>
      <dc:creator>JadhavAj</dc:creator>
      <dc:date>2007-12-19T20:20:07Z</dc:date>
    </item>
    <item>
      <title>Re: Internal cache for S12X</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/Internal-cache-for-S12X/m-p/174355#M6037</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;There's no cache in S12X. You shouldn't do anything to meet your requirement. Writing or reading internal/external RAM isn't cached or queued.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;I believe you shouldn't care about instruction queue. You could need to clear it only&amp;nbsp;hm... &amp;nbsp;if your code runs in paged RAM, you write to RAM paging register and depending on instruction queue size you expect one or more instructions&amp;nbsp;"skipped" on RAM page you are trying to map to...&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 19 Dec 2007 22:58:52 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/Internal-cache-for-S12X/m-p/174355#M6037</guid>
      <dc:creator>kef</dc:creator>
      <dc:date>2007-12-19T22:58:52Z</dc:date>
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