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    <title>S12 / MagniV MicrocontrollersのトピックRe: 9S12G ATD Multi-Channels sample issues</title>
    <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/9S12G-ATD-Multi-Channels-sample-issues/m-p/172158#M5823</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;It is not clear what is expected. You set ATDCTL5_SC bit.&amp;nbsp;Do you expect to&amp;nbsp;get conversion results for&amp;nbsp;special channels, Reserved, Vrh, Vrl, etc?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Sun, 26 Dec 2010 01:58:45 GMT</pubDate>
    <dc:creator>kef</dc:creator>
    <dc:date>2010-12-26T01:58:45Z</dc:date>
    <item>
      <title>9S12G ATD Multi-Channels sample issues</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/9S12G-ATD-Multi-Channels-sample-issues/m-p/172157#M5822</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Expert,&lt;/P&gt;&lt;P&gt;I use 9S12G ATD Multi-Channels sample feature but the result is not&amp;nbsp;as expected.&amp;nbsp;AN0~AN8 will be sampled during each ATD multi-channels conversion. I read register ATDDRn and ATDDRn are not correct after conversion is completed. Please help analyze the issue.&lt;/P&gt;&lt;P&gt;/* ===========================================================================&lt;BR /&gt;*&amp;nbsp;&amp;nbsp; Function:&amp;nbsp;&amp;nbsp; ATD &amp;nbsp;initial&lt;BR /&gt;* ========================================================================= */&lt;/P&gt;&lt;P&gt;void ADC_MultInit(void)&lt;/P&gt;&lt;P&gt;{&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; ATDCTL0=ATDCTL0_WRAP3_MASK;&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; ATDCTL1=0x00;&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; ATDCTL2=0x00;&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; ATDCTL3=ATDCTL3_DJM_MASK +ATDCTL3_S8C_MASK+ATDCTL3_S1C_MASK;&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; ATDCTL4=ATDCTL4_PRS2_MASK;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; ATDDIEN = (u16)(ATDDIEN_IEN9_MASK + ATDDIEN_IEN10_MASK + ATDDIEN_IEN11_MASK);&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; ATDCTL5=ATDCTL5_SC_MASK + ATDCTL5_MULT_MASK;&amp;nbsp; /*Start mult convert*/&lt;BR /&gt;}&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;#define ATDDR_PTR(channel)&amp;nbsp; *(ATDDR_ARR + (channel))&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;/* ===========================================================================&lt;BR /&gt;*&amp;nbsp;&amp;nbsp; Function:&amp;nbsp;&amp;nbsp; Read ATD convert value one by one&lt;BR /&gt;*&lt;BR /&gt;* ========================================================================= */&lt;BR /&gt;void ADC_Service(void)&lt;BR /&gt;{&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; if (ATDSTAT0_SCF)&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; {&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; for (ucIndex=0;ucIndex&amp;lt;eADC_MAX;ucIndex++)&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; {&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; /*Save current conversion value to average buffer*/&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; stAdcBufferObj_s[ucIndex].aucAdcAvgCnt[0]=(u8)ATDDR_PTR(ucIndex);&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; }&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; ATDSTAT0_SCF = 1;&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; }&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; ATDCTL5=ATDCTL5_SC_MASK + ATDCTL5_MULT_MASK;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; /*Mult convert go on*/&lt;BR /&gt;}&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 24 Dec 2010 15:44:10 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/9S12G-ATD-Multi-Channels-sample-issues/m-p/172157#M5822</guid>
      <dc:creator>grace</dc:creator>
      <dc:date>2010-12-24T15:44:10Z</dc:date>
    </item>
    <item>
      <title>Re: 9S12G ATD Multi-Channels sample issues</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/9S12G-ATD-Multi-Channels-sample-issues/m-p/172158#M5823</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;It is not clear what is expected. You set ATDCTL5_SC bit.&amp;nbsp;Do you expect to&amp;nbsp;get conversion results for&amp;nbsp;special channels, Reserved, Vrh, Vrl, etc?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sun, 26 Dec 2010 01:58:45 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/9S12G-ATD-Multi-Channels-sample-issues/m-p/172158#M5823</guid>
      <dc:creator>kef</dc:creator>
      <dc:date>2010-12-26T01:58:45Z</dc:date>
    </item>
    <item>
      <title>Re: 9S12G ATD Multi-Channels sample issues</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/9S12G-ATD-Multi-Channels-sample-issues/m-p/172159#M5824</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Kef,&lt;/P&gt;&lt;P&gt;Thanks. You reminds&amp;nbsp;me. ATDCTL5_SC bit should not be set.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 27 Dec 2010 19:52:28 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/9S12G-ATD-Multi-Channels-sample-issues/m-p/172159#M5824</guid>
      <dc:creator>grace</dc:creator>
      <dc:date>2010-12-27T19:52:28Z</dc:date>
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