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    <title>topic Re: S12X EBI in S12 / MagniV Microcontrollers</title>
    <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/S12X-EBI/m-p/168840#M5568</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;Hello,&lt;BR /&gt;&lt;BR /&gt;The RAM area mentioned is for "internal" memory.&lt;BR /&gt;If you wish to add external RAM, you will therefore address in the EXTERNAL SPACE.&lt;BR /&gt;&lt;BR /&gt;Note that the XGATE cannot access external space.&lt;BR /&gt;The ALIGN 2 is only necessary when XGATE can access the area because XGATE can only do ALIGNED 16-BIT accesses, while the CPU can do mis-aligned accesses.&lt;BR /&gt;&lt;BR /&gt;Therefore, when you declare your external RAM in the external space, you will not be able to access it from the XGATE and will not need the ALIGN in the prm. This will save you space if you store 8-Bit variables (for instance).&lt;BR /&gt;&lt;BR /&gt;Alban.&lt;BR /&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 04 Dec 2007 09:03:35 GMT</pubDate>
    <dc:creator>Nabla69</dc:creator>
    <dc:date>2007-12-04T09:03:35Z</dc:date>
    <item>
      <title>S12X EBI</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/S12X-EBI/m-p/168835#M5563</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;Hi,&lt;/DIV&gt;&lt;DIV&gt;Is there any reference design about using RAM (16 bit) on EBI (especially hardware connections)? Or documents about this article?&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 30 Nov 2007 18:00:57 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/S12X-EBI/m-p/168835#M5563</guid>
      <dc:creator>sfb</dc:creator>
      <dc:date>2007-11-30T18:00:57Z</dc:date>
    </item>
    <item>
      <title>Re: S12X EBI</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/S12X-EBI/m-p/168836#M5564</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;&lt;A href="http://www.freescale.com/files/microcontrollers/doc/app_note/AN2708.pdf" rel="nofollow" target="_blank"&gt;http://www.freescale.com/files/microcontrollers/doc/app_note/AN2708.pdf&lt;/A&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 30 Nov 2007 18:20:00 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/S12X-EBI/m-p/168836#M5564</guid>
      <dc:creator>kef</dc:creator>
      <dc:date>2007-11-30T18:20:00Z</dc:date>
    </item>
    <item>
      <title>Re: S12X EBI</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/S12X-EBI/m-p/168837#M5565</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;Hi,&lt;/DIV&gt;&lt;DIV&gt;Thanks for reply. And one more question:&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;When I created a new project with 9S12XDP512 with XGATE in RAM option and banked memory I saw in prm file :&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;RAM_F9&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; = READ_WRITE&amp;nbsp; 0xF91000 TO 0xF91FFF&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;For 0xF91000 address, which part is belong to RPAGE and which part is CPU address. I know that CPU address part ise 12 bit (11:0), RPAGE ise 8 bit (12:19) and 000 (20:22).&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sat, 01 Dec 2007 00:26:10 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/S12X-EBI/m-p/168837#M5565</guid>
      <dc:creator>sfb</dc:creator>
      <dc:date>2007-12-01T00:26:10Z</dc:date>
    </item>
    <item>
      <title>Re: S12X EBI</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/S12X-EBI/m-p/168838#M5566</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;Hiya,&lt;BR /&gt;&lt;BR /&gt;0x1FFF is the 16-bit address for the "local" = "CPU".&lt;BR /&gt;&lt;BR /&gt;The higher part = "0xF9" is the content of the PAGING.&lt;BR /&gt;&lt;BR /&gt;Look at Figure 1-4. S12X CPU &amp;amp; BDM Global Address Mapping&lt;BR /&gt;From datasheet p°41 of MC9S12XDP512.&lt;BR /&gt;&lt;BR /&gt;Cheers,&lt;BR /&gt;Alban.&lt;BR /&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sat, 01 Dec 2007 01:37:21 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/S12X-EBI/m-p/168838#M5566</guid>
      <dc:creator>Nabla69</dc:creator>
      <dc:date>2007-12-01T01:37:21Z</dc:date>
    </item>
    <item>
      <title>Re: S12X EBI</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/S12X-EBI/m-p/168839#M5567</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV align="left"&gt;&lt;FONT color="#0000ff" face="Arial" size="2"&gt;&lt;SPAN class="670003408-03122007"&gt;Hi,&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/DIV&gt;&lt;DIV align="left"&gt;&lt;FONT color="#0000ff" face="Arial" size="2"&gt;&lt;SPAN class="670003408-03122007"&gt;I created sample project with CodeWarrior and checked the prm file (prm was created by Code Warrior for S12XDP512 with XGATE in RAM and banked memory model options). I saw that RAM area is:&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;FONT color="#0000ff" face="Arial" size="2"&gt;&lt;/FONT&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN class="670003408-03122007"&gt;&lt;FONT color="#0000ff" face="Arial" size="2"&gt;---------------------------------------------------------------------------------------------------------------&lt;/FONT&gt;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV align="left"&gt;&lt;FONT color="#0000ff" face="Arial" size="2"&gt;&lt;SPAN class="670003408-03122007"&gt;RAM_XGATE_STK = READ_WRITE&amp;nbsp; 0xF81000 TO 0xF810FF;&lt;BR /&gt;RAM_F8&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; = READ_WRITE&amp;nbsp; 0xF81100 TO 0xF81FFF ALIGN 2[1:1];&lt;BR /&gt;RAM_F9&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; = READ_WRITE&amp;nbsp; 0xF91000 TO 0xF91FFF ALIGN 2[1:1];&lt;BR /&gt;RAM_FA&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; = READ_WRITE&amp;nbsp; 0xFA1000 TO 0xFA1FFF ALIGN 2[1:1];&lt;BR /&gt;RAM_FB&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; = READ_WRITE&amp;nbsp; 0xFB1000 TO 0xFB1FFF ALIGN 2[1:1];&lt;BR /&gt;RAM_FC&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; = READ_WRITE&amp;nbsp; 0xFC1000 TO 0xFC1FFF ALIGN 2[1:1];&lt;BR /&gt;RAM_FD&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; = READ_WRITE&amp;nbsp; 0xFD1000 TO 0xFD1FFF ALIGN 2[1:1];&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;FONT color="#0000ff" face="Arial" size="2"&gt;&lt;SPAN class="670003408-03122007"&gt;&lt;FONT color="#0000ff" face="Arial" size="2"&gt;---------------------------------------------------------------------------------------------------------------&lt;/FONT&gt;&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/DIV&gt;&lt;FONT size="+0"&gt;&lt;SPAN class="670003408-03122007"&gt;&lt;/SPAN&gt;&lt;/FONT&gt;&lt;DIV align="left"&gt;&lt;BR /&gt;&lt;FONT color="#0000ff" face="Arial" size="2"&gt;-According to AN2734 on page 6&lt;BR /&gt;Memory Address Bits = 000 PPPP PPPP aaaa aaaa aaaa&lt;BR /&gt;Global Address Range = $00_0000 to $0F_FFFF&lt;BR /&gt;I couldn't understand the relation between Global Address Range, Memory Address Bits and&lt;BR /&gt;above prm file.&lt;/FONT&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;FONT color="#0000ff" face="Arial" size="2"&gt;&lt;/FONT&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV align="left"&gt;&lt;FONT color="#0000ff" face="Arial" size="2"&gt;-I want to use two external RAM (256K 16 bits). How can I organise them?&lt;/FONT&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 03 Dec 2007 16:43:15 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/S12X-EBI/m-p/168839#M5567</guid>
      <dc:creator>sfb</dc:creator>
      <dc:date>2007-12-03T16:43:15Z</dc:date>
    </item>
    <item>
      <title>Re: S12X EBI</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/S12X-EBI/m-p/168840#M5568</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;Hello,&lt;BR /&gt;&lt;BR /&gt;The RAM area mentioned is for "internal" memory.&lt;BR /&gt;If you wish to add external RAM, you will therefore address in the EXTERNAL SPACE.&lt;BR /&gt;&lt;BR /&gt;Note that the XGATE cannot access external space.&lt;BR /&gt;The ALIGN 2 is only necessary when XGATE can access the area because XGATE can only do ALIGNED 16-BIT accesses, while the CPU can do mis-aligned accesses.&lt;BR /&gt;&lt;BR /&gt;Therefore, when you declare your external RAM in the external space, you will not be able to access it from the XGATE and will not need the ALIGN in the prm. This will save you space if you store 8-Bit variables (for instance).&lt;BR /&gt;&lt;BR /&gt;Alban.&lt;BR /&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 04 Dec 2007 09:03:35 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/S12X-EBI/m-p/168840#M5568</guid>
      <dc:creator>Nabla69</dc:creator>
      <dc:date>2007-12-04T09:03:35Z</dc:date>
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