<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>S12 / MagniV MicrocontrollersのトピックRe: 9S12XDP512: Question about the three SPI's</title>
    <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/9S12XDP512-Question-about-the-three-SPI-s/m-p/162487#M5175</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;The three sets of registers should also be defined within the header file for the MC9S12XDP512.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Mac&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 16 Mar 2009 12:24:38 GMT</pubDate>
    <dc:creator>bigmac</dc:creator>
    <dc:date>2009-03-16T12:24:38Z</dc:date>
    <item>
      <title>9S12XDP512: Question about the three SPI's</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/9S12XDP512-Question-about-the-three-SPI-s/m-p/162485#M5173</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I have read the datasheet for the MC9S12XDP512 on the SPI section.&amp;nbsp; There is only one memory map for the SPI.&amp;nbsp; Does this mean that if I&amp;nbsp;set the SPE in the in the SPICR1 register, it will turn on all three SPI's of the MCU?&amp;nbsp; Also, does this mean that they will use the same SPIDR register?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;If this is the case, then there is no sense in making three SPI ports when I could just connect multiple devices to one SPI port and select each one utilizing the slave select signal.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I have tried to look for application notes on this but could not find any.&amp;nbsp; What I want to know is, are there separate memory maps for each SPI in this MCU so that each SPI could have its own clock rate and its own data line?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I appreciate any help.&amp;nbsp; Thanks.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 16 Mar 2009 04:16:18 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/9S12XDP512-Question-about-the-three-SPI-s/m-p/162485#M5173</guid>
      <dc:creator>DavidN_</dc:creator>
      <dc:date>2009-03-16T04:16:18Z</dc:date>
    </item>
    <item>
      <title>Re: 9S12XDP512: Question about the three SPI's</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/9S12XDP512-Question-about-the-three-SPI-s/m-p/162486#M5174</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;What datasheet are you using? MC9S12XDP512&amp;nbsp; Data Sheet Rev 2.17 Table 1-1. Device Register Memory Map: 0x00D8-0x00DF - SPI0, 0x00F0-00F7 - SPI1, 0x00F8-0x00FF - SPI2&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 16 Mar 2009 12:01:37 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/9S12XDP512-Question-about-the-three-SPI-s/m-p/162486#M5174</guid>
      <dc:creator>kef</dc:creator>
      <dc:date>2009-03-16T12:01:37Z</dc:date>
    </item>
    <item>
      <title>Re: 9S12XDP512: Question about the three SPI's</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/9S12XDP512-Question-about-the-three-SPI-s/m-p/162487#M5175</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;The three sets of registers should also be defined within the header file for the MC9S12XDP512.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Mac&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 16 Mar 2009 12:24:38 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/9S12XDP512-Question-about-the-three-SPI-s/m-p/162487#M5175</guid>
      <dc:creator>bigmac</dc:creator>
      <dc:date>2009-03-16T12:24:38Z</dc:date>
    </item>
    <item>
      <title>Re: 9S12XDP512: Question about the three SPI's</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/9S12XDP512-Question-about-the-three-SPI-s/m-p/162488#M5176</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;Ah sorry.&amp;nbsp; It was in Appendix G on page 1322.&amp;nbsp; Never thought to look that far..&amp;nbsp; My mistake.&amp;nbsp; Sorry to bother.&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 16 Mar 2009 12:26:31 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/9S12XDP512-Question-about-the-three-SPI-s/m-p/162488#M5176</guid>
      <dc:creator>DavidN_</dc:creator>
      <dc:date>2009-03-16T12:26:31Z</dc:date>
    </item>
  </channel>
</rss>

