S12 / MagniV MicrocontrollersのトピックRe: PWM module and Timer module

PWM module and Timer module

francisco_grame — Tue, 16 Aug 2011 04:03:34 GMT

Hi,

I am using a MC9S1264MFA microcontroler. I was trying use PWM2 channel and the timer 2 interrupt, can I use two function at same time?

I do this question because, PWM channel 2 working normally but timer 2 don´t work like I configured .

PWM channel 2 configuration:

    MODRR = 0x14;
    PWME = 0;
    PWMPOL = 0x14;
    PWMCLK = 0x14;
    PWMPRCLK = 0x00;
    PWMSCLA = 0x0C;
    PWMSCLB = 0x0C;
    PWMCAE = 0x00;

    PWMPER and PWMDTY was dynamically configured.

Timer 2 configuration:

    TSCR2     =     0x84;
    TSCR1    =     0x80;
    TIOS     |=     0x04;
    TIE        |=     0x04;
    TC2        =    0x01;
    TCTL2    &=    0xCF;
    TCTL4    &=    0xCF;
    TFLG1    |=    0x04;

I´m trying configure to 0,666us, but the interrupt occur every 0,042ms.
what I´m doing wrong?

Re: PWM module and Timer module

kef — Tue, 16 Aug 2011 14:05:22 GMT

Could you please decifier all those numbers? It is not clear without datasheet what bits are you setting and what bits are you clearing.

Regarding timing, you didn't say what is crystal clock and if you are using PLL or not.

Re: PWM module and Timer module

francisco_grame — Tue, 16 Aug 2011 18:54:23 GMT

Cristal: 8Mhz

PLL: 48Mhz

PWM channel 2 configuration:

MODRR = 0x14; //port pin 2 and 4 was connected to pwm 2 and 4 output

PWME = 0; //PWM enable - disable initially

PWMPOL = 0x14; // pwm polarity

PWMCLK = 0x14; //clock select SA and SB selected

PWMPRCLK = 0x00; //bus prescaler select, using none

PWMSCLA = 0x0C; // pwm clock = SA clock/(2*PWMSCLA) = 24MHz/24 = 1 us clk

PWMSCLB = 0x0C; // pwm clock = SA clock/(2*PWMSCLA) = 24MHz/24 = 1 us clk

PWMCAE = 0x00; //pwm left aligned

PWMPER and PWMDTY was dynamically configured.

Timer 2 configuration:

TSCR2 = 0x84; //TIMER overflow interrupt enable and timer prescaler = 16, (time clock = (48MHz /2) / 16 = 0,666us)

TSCR1 = 0x80; //Timer enable

TIOS |= 0x04; //timer 2 channel is output compare

TIE |= 0x04; // timer 2 interrupt enable

TC2 = 0x01; // timer 2 output compare resgister, match every 1 count of timer (TCNT), TC2 was updated on code.

TCTL2 &= 0xCF; // timer control register, disconect timer 2 from output pin logic

TCTL4 &= 0xCF; // Capture disabled

TFLG1 |= 0x04; // Clear Timer2 flag (interrupt flag)

I´m trying configure to 0,666us, but the interrupt occur every 0,042ms. what I´m doing wrong?

Re: PWM module and Timer module

kef — Wed, 17 Aug 2011 02:16:50 GMT

Much better now, please mention bit names next time.

Timer compare is always available, you just can't output both signals to the same pin. With MODRR bit set you can see on PTT PWM output, but not the timer compare output.

If I understood you intentions, you are trying to generate timer interrupt every 16 bus clock cycles. Interrupt entry and exit with RTI takes longer than that! That means that you are always late writing new compare value to timer register and interrupt happens not every timer tick, but roughly every 2^16 timer ticks, which is about 0.04s. Are you really observing 0.04ms period and not 0.04s?

TFLG1 |= 0x04; // Clear Timer2 flag (interrupt flag)

^^ comment is wrong. You are clearing all timer TFLG1 flags, not just 2nd channel flag. To clear just 2nd flag use one of these:

TFLG1 = 0x04;

TFLG1 &= 0x04; // please don't mix with bit clear code like TFLG1 &= ~0x04;

Re: PWM module and Timer module

francisco_grame — Wed, 17 Aug 2011 03:40:28 GMT

Sorry for my incomplete post.

Well, you really is correct, the period is 0.045s. If I understand, when I use RTI I can´t obtain periods less than 0,045ms.

It´s so bad, I was trying this for three days.

Ok, Can you tell me if I have other option to make frequency with 200khz or period with 4us.

I have only timer 2 and 4. I think not.

Thanks for your help.

Best Regards

Re: PWM module and Timer module

francisco_grame — Wed, 17 Aug 2011 19:01:01 GMT

Ops, I said 0.045ms instead 0.045s.

I actually wanted a pwm period at least 200 Hz with resolution at least 255.

Underlining that I haven´t hardware pwm channel available.

Re: PWM module and Timer module

kef — Wed, 17 Aug 2011 21:14:43 GMT

Least RTI divider is 2^10=1024. RTI source clock is your crystal clock, so 1(8MHz/1024)=128us. You probably assumed that RTI is clocked from bus clock, 128/(24/8)=42.6us, right?

200kHz is 120 bus cycles @ 24MHz bus clock. 120 is not a lot, but that's enough to service interrupt, of course you should keep you ISR code short in terms of execution time.

You can generate 200kHz using just hardware, without any CPU load. PWM is well suited for this. You need to program PWM period register for 120 bus cycles and set up duty cycle register for less than 120 bus cycles.
You can generate 200kHz also using timer. For no CPU load you can make timer counter reset on TC7 compare (see TCRE bit). You program TC7 period for 120 bus cycles and use OC7M and OC7D registers to clear(set) pin, while other than TC7 channel is set up to set(clear) pin on compare match. TC7 does one edge, another TCx does another edge. But using timer this way may be a pain to use other channels for other purposes, since timer counter never will go past 120.

But you don't load CPU, no single interrupt is required.

Less restricting but more CPU execution time hungry is generating interrupt for each edge of the waveform. Each time you enter interrupt you set up next timer: change TCTLx configuration and calculate next TCx value TCx = TCx + n;

Ops, I said 0.045ms instead 0.045s

really? Certainly you can have RTI interrupts more often than each 0.045s.

Yes, you can do PWM using timer. It would be best to use TCRE=1 approach for this, because using interrupts you are limited on time between two adjacent edges. It can't be too short, because CPU needs time to enter and exit ISR. So duty cycle can't be too close to 0% and too close to 100%.

Re: PWM module and Timer module

francisco_grame — Fri, 19 Aug 2011 08:09:26 GMT

Thanks for your help.

These information helped me alot.

Best Regards.