9S12NE64 CPU resets when EPHYEN is enabled

LT — Fri, 16 May 2008 06:46:59 GMT

Hello,
I am having a problem where the 9S12NE CPU resets when EPHYEN bit is set. I have allocated RAM space for the Rx buffers and Txbuffer.
RAM starts at $2000.
RxbufferA is at $2000, RxbufferB is at $2200 and Txbuffer is at $2300.( all buffers are 256 long )
I have a little more than 5K of RAM left for the application.
The EMACE bit is disabled.
Any hints to the problem will be much appreciated.
Thanks,
LT

Re: 9S12NE64 CPU resets when EPHYEN is enabled

mjbcswitzerland — Thu, 22 May 2008 02:50:13 GMT

Hi LT

Have you respected the start up sequence including delays?
Example:
EPHYCTL1 = PHY_ADDRESS;
EPHYCTL0 = 0;                                                   // enable autonegotiate
EPHYCTL0 |= LEDEN;                                       // enable LED support in the Hardware
EPHYSR = EPHYIF;                                           // clear interrupt
EPHYCTL0 |= (EPHYEN | EPHYIEN);              // enable PHY with interrupt
for (usDelay=64000; usDelay >0; usDelay--); // delay before continuing
SWRST = MACRST;                                           // EMAC software reset
for (usDelay=16; usDelay >0; usDelay--);        // short wait
MCMST = (BUS_CLOCK/5000000);                 // set up MDC clock to 2.5MHz
... set up memory use, etc.

Regards

Mark

www.uTasker.com

topic Re: 9S12NE64 CPU resets when EPHYEN is enabled in S12 / MagniV Microcontrollers

9S12NE64 CPU resets when EPHYEN is enabled

Re: 9S12NE64 CPU resets when EPHYEN is enabled