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    <title>S12 / MagniV MicrocontrollersのトピックRe: S12XDP512 pulse accumulator B missing control bits</title>
    <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/S12XDP512-pulse-accumulator-B-missing-control-bits/m-p/152214#M4400</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;Hello&lt;BR /&gt;&lt;BR /&gt;Pulse Accumulator B operates in event counter mode (implied in figure 7-70)&lt;BR /&gt;EDG0B and EDG0A in TCTL4 determine the active edge for the 16-bit pulse accumulator PACB.&lt;BR /&gt;&lt;BR /&gt;The documentation is indeed not very clear.&lt;BR /&gt;This shall be included on a list of improvements for future versions.&lt;BR /&gt;&lt;BR /&gt;DPB&lt;BR /&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 08 May 2008 16:34:30 GMT</pubDate>
    <dc:creator>DPB</dc:creator>
    <dc:date>2008-05-08T16:34:30Z</dc:date>
    <item>
      <title>S12XDP512 pulse accumulator B missing control bits</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/S12XDP512-pulse-accumulator-B-missing-control-bits/m-p/152213#M4399</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt; &lt;/DIV&gt;&lt;SPAN&gt;The PBCTL register is missing a few of the control bits that PACTL has in the Enhanced Capture Timer. I can't find in the data sheet what mode it defaults to. Specifically, PAMOD (event counter or gated time accumulation), and PEDGE (which edge to trigger on). Thanks&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 01 May 2008 01:56:40 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/S12XDP512-pulse-accumulator-B-missing-control-bits/m-p/152213#M4399</guid>
      <dc:creator>shedmeister</dc:creator>
      <dc:date>2008-05-01T01:56:40Z</dc:date>
    </item>
    <item>
      <title>Re: S12XDP512 pulse accumulator B missing control bits</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/S12XDP512-pulse-accumulator-B-missing-control-bits/m-p/152214#M4400</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;Hello&lt;BR /&gt;&lt;BR /&gt;Pulse Accumulator B operates in event counter mode (implied in figure 7-70)&lt;BR /&gt;EDG0B and EDG0A in TCTL4 determine the active edge for the 16-bit pulse accumulator PACB.&lt;BR /&gt;&lt;BR /&gt;The documentation is indeed not very clear.&lt;BR /&gt;This shall be included on a list of improvements for future versions.&lt;BR /&gt;&lt;BR /&gt;DPB&lt;BR /&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 08 May 2008 16:34:30 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/S12XDP512-pulse-accumulator-B-missing-control-bits/m-p/152214#M4400</guid>
      <dc:creator>DPB</dc:creator>
      <dc:date>2008-05-08T16:34:30Z</dc:date>
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