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    <title>S12 / MagniV MicrocontrollersのトピックVGA controller (MC9S12XEP100)</title>
    <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/VGA-controller-MC9S12XEP100/m-p/146502#M3997</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;I am attempting to use the MC9S12XEP100 to control a VGA monitor as part of a university project. I need to shift out bytes of data (through a port in parallel) at a frequency of 3.15 MHz. I have set the bus frequency to 50 MHz giving me 16 cycles per byte.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;In that 16 cycles&amp;nbsp;I need to increment a couple of counter variables, perform a couple of logical tests and shift a byte of data out. In addition I would either have to use an interrupt or at least check for a timer flag.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;My question is, does this sound at all possible using the main CPU. From reading the CPU RM i found that many simple assembly instructions require at least a couple of bus cycles. Therefore it doesnt sound likely to me.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;An alternative would be to use the XGATE. Would this be benefitial? My guess is that many cycles would be required to deal with the interrupt epilogue/prologue and the gained cycles could be lost.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;How do XGATE instruction compare in execution time to CPU ones with regards to the simple tasks above.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Many Thanks for any help&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 27 Jan 2009 06:54:16 GMT</pubDate>
    <dc:creator>ernestsnaith</dc:creator>
    <dc:date>2009-01-27T06:54:16Z</dc:date>
    <item>
      <title>VGA controller (MC9S12XEP100)</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/VGA-controller-MC9S12XEP100/m-p/146502#M3997</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;I am attempting to use the MC9S12XEP100 to control a VGA monitor as part of a university project. I need to shift out bytes of data (through a port in parallel) at a frequency of 3.15 MHz. I have set the bus frequency to 50 MHz giving me 16 cycles per byte.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;In that 16 cycles&amp;nbsp;I need to increment a couple of counter variables, perform a couple of logical tests and shift a byte of data out. In addition I would either have to use an interrupt or at least check for a timer flag.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;My question is, does this sound at all possible using the main CPU. From reading the CPU RM i found that many simple assembly instructions require at least a couple of bus cycles. Therefore it doesnt sound likely to me.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;An alternative would be to use the XGATE. Would this be benefitial? My guess is that many cycles would be required to deal with the interrupt epilogue/prologue and the gained cycles could be lost.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;How do XGATE instruction compare in execution time to CPU ones with regards to the simple tasks above.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Many Thanks for any help&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 27 Jan 2009 06:54:16 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/VGA-controller-MC9S12XEP100/m-p/146502#M3997</guid>
      <dc:creator>ernestsnaith</dc:creator>
      <dc:date>2009-01-27T06:54:16Z</dc:date>
    </item>
    <item>
      <title>Re: VGA controller (MC9S12XEP100)</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/VGA-controller-MC9S12XEP100/m-p/146503#M3998</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;XGATE is likely a good choice for this application but it depends on your software architecture.&lt;BR /&gt;XGATE performs most arithmetic (shift, add, parity) functions much more quickly than the CPU when executing from RAM and has much shorter event prolog/epilog times. However, it has the same overhead when writing to the I/O because that timing is fixed to the CPU bs speed.&lt;BR /&gt;Have a look at &lt;A href="http://www.freescale.com/files/microcontrollers/doc/app_note/AN3493.pdf" rel="nofollow" target="_blank"&gt;AN3493&lt;/A&gt; which performs a similar task.&lt;BR /&gt;You can write the application task in C and then run it on each core in turn to see which is the more efficient.&lt;BR /&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 27 Jan 2009 19:09:50 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/VGA-controller-MC9S12XEP100/m-p/146503#M3998</guid>
      <dc:creator>Steve</dc:creator>
      <dc:date>2009-01-27T19:09:50Z</dc:date>
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