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    <title>S12 / MagniV MicrocontrollersのトピックS12XDP512 -  How to use external RAM on CS2 in conjuction with ROMHM bit</title>
    <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/S12XDP512-How-to-use-external-RAM-on-CS2-in-conjuction-with/m-p/141234#M3238</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;SPAN&gt;Hi Forum,&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;we have an external RAM connected to CS2 chip select.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;This select the external RAM on address $14_0000&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;To get an access to this memory we set the ROMHM=1&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;(as mentioned in DataSheet rev 2.15 p. 674)&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Using this setup, it seems that this CS2 is in collision with&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;the internal Flash placed at address $14_4000.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;How to set the ROMHM bit to get right access to this&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;external RAM?&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;How should we access the internal Flash page $4000-$7fff?&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Thanks for your help&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Regards&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Paul&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;DIV&gt; &lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 26 Jul 2007 15:46:19 GMT</pubDate>
    <dc:creator>pufi</dc:creator>
    <dc:date>2007-07-26T15:46:19Z</dc:date>
    <item>
      <title>S12XDP512 -  How to use external RAM on CS2 in conjuction with ROMHM bit</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/S12XDP512-How-to-use-external-RAM-on-CS2-in-conjuction-with/m-p/141234#M3238</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;SPAN&gt;Hi Forum,&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;we have an external RAM connected to CS2 chip select.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;This select the external RAM on address $14_0000&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;To get an access to this memory we set the ROMHM=1&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;(as mentioned in DataSheet rev 2.15 p. 674)&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Using this setup, it seems that this CS2 is in collision with&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;the internal Flash placed at address $14_4000.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;How to set the ROMHM bit to get right access to this&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;external RAM?&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;How should we access the internal Flash page $4000-$7fff?&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Thanks for your help&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Regards&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Paul&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;DIV&gt; &lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 26 Jul 2007 15:46:19 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/S12XDP512-How-to-use-external-RAM-on-CS2-in-conjuction-with/m-p/141234#M3238</guid>
      <dc:creator>pufi</dc:creator>
      <dc:date>2007-07-26T15:46:19Z</dc:date>
    </item>
    <item>
      <title>Re: S12XDP512 -  How to use external RAM on CS2 in conjuction with ROMHM bit</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/S12XDP512-How-to-use-external-RAM-on-CS2-in-conjuction-with/m-p/141235#M3239</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;BR /&gt;&lt;/DIV&gt;&lt;BLOCKQUOTE&gt;&lt;DIV&gt;&lt;HR /&gt;&lt;/DIV&gt;&lt;DIV&gt;pufi wrote:&lt;BR /&gt;Hi Forum,&lt;BR /&gt;&lt;BR /&gt;we have an external RAM connected to CS2 chip select.&lt;BR /&gt;This select the external RAM on address $14_0000&lt;BR /&gt;&lt;/DIV&gt;&lt;DIV&gt;To get an access to this memory we set the ROMHM=1&lt;BR /&gt;(as mentioned in DataSheet rev 2.15 p. 674)&lt;BR /&gt;&lt;BR /&gt;Using this setup, it seems that this CS2 is in collision with&lt;BR /&gt;the internal Flash placed at address $14_4000.&lt;BR /&gt;&lt;/DIV&gt;&lt;/BLOCKQUOTE&gt;&lt;DIV&gt;I wonder what collision could you observe? Do you see all FFFF's at $4000..$7FFF? Maybe it's read-only instead of read-write? BTW, is external memory bus really enabled?&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;BLOCKQUOTE&gt;&lt;DIV&gt;&lt;BR /&gt;How to set the ROMHM bit to get right access to this&lt;BR /&gt;external RAM?&lt;BR /&gt;&lt;/DIV&gt;&lt;/BLOCKQUOTE&gt;&lt;DIV&gt;MMCCTL1 |= 2;&amp;nbsp; // something like this probably?&lt;/DIV&gt;&lt;BLOCKQUOTE&gt;&lt;DIV&gt;&lt;BR /&gt;How should we access the internal Flash page $4000-$7fff?&lt;BR /&gt;&lt;BR /&gt;&lt;/DIV&gt;&lt;/BLOCKQUOTE&gt;&lt;DIV&gt;$4000-$7FFF is accessible using global memory addressing at $7F_4000..$7F_7FFF or in the PPAGE paged memory window at $8000..$BFFF when PPAGE==$FD&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Regards&lt;BR /&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;BR /&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 26 Jul 2007 17:30:24 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/S12XDP512-How-to-use-external-RAM-on-CS2-in-conjuction-with/m-p/141235#M3239</guid>
      <dc:creator>kef</dc:creator>
      <dc:date>2007-07-26T17:30:24Z</dc:date>
    </item>
    <item>
      <title>Re: S12XDP512 -  How to use external RAM on CS2 in conjuction with ROMHM bit</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/S12XDP512-How-to-use-external-RAM-on-CS2-in-conjuction-with/m-p/141236#M3240</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;Hi Kef,&lt;BR /&gt;&lt;BR /&gt;thanks for your help,&lt;BR /&gt;&lt;BR /&gt;But I still do not understant correctly the ROMHM bit.&lt;BR /&gt;Why do I need to switch this bit to 1 when I access the external RAM on CS2?&lt;BR /&gt;&lt;BR /&gt;In my setup I set the ROMHM=0 and the external access&lt;BR /&gt;works on the address $14_4000.&lt;BR /&gt;&lt;BR /&gt;But the address area 14_0000 - 14_3FFF returns wrong values (not a FF's)&lt;BR /&gt;&lt;BR /&gt;I think that the s12DPx512 data sheet ont the p. 674 is not correct.&lt;BR /&gt;In case of the external acces the&amp;nbsp; ROMHM bit&amp;nbsp; should be set to&amp;nbsp; 0 and not to 1.&lt;BR /&gt;&lt;BR /&gt;Regards&lt;BR /&gt;Paul&lt;BR /&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 27 Jul 2007 15:41:35 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/S12XDP512-How-to-use-external-RAM-on-CS2-in-conjuction-with/m-p/141236#M3240</guid>
      <dc:creator>pufi</dc:creator>
      <dc:date>2007-07-27T15:41:35Z</dc:date>
    </item>
    <item>
      <title>Re: S12XDP512 -  How to use external RAM on CS2 in conjuction with ROMHM bit</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/S12XDP512-How-to-use-external-RAM-on-CS2-in-conjuction-with/m-p/141237#M3241</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;You don't have to touch ROMHM to access external RAM on CS2. ROMHM controls only what is mapped from global memory map to CPU local addresses $4000.7FFF.&amp;nbsp;ROMHM=0 maps flash page $FD to 4000-7fff. ROMHM=1 maps to 4000..7FFF global addresses 14_4000..14_7FFF, which&amp;nbsp;are external memory (on CS2 if enabled).&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;You write that 14_0000..14_3FFF don't return FFs. I think it's normal. It's external memory. I would expect FFs here if it was erased flash or just pullups on data lines.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Table on page 674 tells what is mapped to CPU's local addresses $4000..$7FFF from global memory, not what is mapped from 4000-7fff to global memory. It's correct:&amp;nbsp;ROMHM=0 means flash page $FD is mapped to $4000.7FFF.&amp;nbsp;ROMHM=1 means external memory (14_4000-14_7FFF) is mapped to $4000-$7FFF.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Hope I understood your questions&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 27 Jul 2007 18:07:36 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/S12XDP512-How-to-use-external-RAM-on-CS2-in-conjuction-with/m-p/141237#M3241</guid>
      <dc:creator>kef</dc:creator>
      <dc:date>2007-07-27T18:07:36Z</dc:date>
    </item>
    <item>
      <title>Re: S12XDP512 -  How to use external RAM on CS2 in conjuction with ROMHM bit</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/S12XDP512-How-to-use-external-RAM-on-CS2-in-conjuction-with/m-p/141238#M3242</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;Hi Kef,&lt;BR /&gt;&lt;BR /&gt;you are right, your setup works.&lt;BR /&gt;Thanx!&lt;BR /&gt;&lt;BR /&gt;I summarize:&lt;BR /&gt;&lt;BR /&gt;&amp;nbsp;When the ROMHM=0 then the 16k FLASH page at address 0x7F4000 is mapped in to the address 0x4000. With other words, the FLASH page 0x7F4000 (PPAGE=0xFD) is accesible at address 0x4000.&lt;BR /&gt;&lt;BR /&gt;&amp;nbsp;When the ROMHM=1 then the external 16k address space 0x144000-0x147fff is mapped to the address 0x4000.&amp;nbsp; With other words, the external space 0x144000-0x147fff is accessible at address 0x4000.&lt;BR /&gt;&lt;BR /&gt;&amp;nbsp;In both cases is the external space 0x144000-0x147fff accessible with GPAGE register access.&lt;BR /&gt;&lt;BR /&gt;Best regards&lt;BR /&gt;Paul&lt;BR /&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 30 Jul 2007 22:36:55 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/S12XDP512-How-to-use-external-RAM-on-CS2-in-conjuction-with/m-p/141238#M3242</guid>
      <dc:creator>pufi</dc:creator>
      <dc:date>2007-07-30T22:36:55Z</dc:date>
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