Interrupts in XGATE and CPU

RChapman — Sat, 28 Jan 2006 12:35:05 GMT

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Posted: Mon Jan 16, 2006 11:16 am

Hey,

I want to be able to handle certain interrupts on the XGATE, and others on the CPU. Right now I have my program configured so that the XGATE can handle an incoming message on the CAN2 peripheral; that works fine. However, now I want to have the CPU handle the interrupt for the PIT0 I have setup. But when I enable the PIT with: PITCFLMT = 0x80; and I then try to run the program though debug in CodeWarrior, it won't work (I hit Start/Continue, and it immedialy stops with the error: Unknown Event, in the command window.

Here's what my PIT0 looks like at the end of main.c:

Code:

#pragma CODE_SEG __NEAR_SEG NON_BANKED interrupt void PIT0_ISR(void) { //my code here PITTF = 0x01; } #pragma CODE_SEG DEFAULT

Do I need to do something in the XGATE interrupt vector for the PIT0 Channel in my .cxgate file? I've also tried using the ROUTE_INTERRUPT Macro to set RST for the PIT0 to 0 to signify that the CPU should handle the interrupt, but t hat didn't work either.

Does anyone have any suggestions, or maybe an example that handles interrupts on both the XGATE and CPU?

Posted: Mon Jan 16, 2006 12:11 pm

Doesn't sound like a problem to do with the XGATE or the interrupt controller. I'd guess that what's happening is that you enable the interrupts on the CPU & some other interrupt occurs that you don't have a vector for and so the code is running away. Try allocating all the CPU interrupts (except for PIT) to some common handler that you can set a breakpoint on. A common culprit is the IRQ pin. Another suggestion would be double-check that you have initialised the correct PIT vector.
The interrupt allocation between XGATE and CPU is on a by-interrupt basis so what you do on one interrupt doesn't influence the handling of any others.

Good luck!

Posted: Mon Jan 16, 2006 12:20 pm

Is the XGATE Vector Table (the one generated in xgate.cxgate by CodeWarrior) different fromt he CPU's XGATE vector table? How would I allocate all of the CPU interrupts to a common handler, in the same manner that's done in the XGATE vector table? I guess I'm in general a bit confused on the vector table/base and how the CPU redirects an interrupt to the appropriate Handler (normally, you don't have to do anything other than enable interrupts and create the PIT0_ISR function, but implementing all the code to route to the XGATE, something seems to change and I'm not quite sure what's going on...).

Note on something I just tried:

When trying to use the vector table from AN2883SW.zip, I get this linking error: Vector allocated at absolute addres 0xFFFE overlaps with sections placed in segment .absSeg648

I think I just need to setup a correctly working CPU interrupt vector table, but I must be missing something...

Thanks for the quick reply!

Posted: Mon Jan 16, 2006 4:34 pm

Ok, let's see if I can clear this up for you...

There is one vector table for each processor core, so one for the CPU and one for XGATE. In the CW wizard project, the XGATE table is in the xgate.cxgate file and the CPU is in the linker parameter file. So there isn't a

Quote:

CPU's XGATE vector table

only XGATE's vector table and CPU's vector table.

Quote:

How would I allocate all of the CPU interrupts to a common handler, in the same manner that's done in the XGATE vector table?

There are several ways to populate the CPU vector table. Starting from the example you can simply add more vector definitions - look for the VECTOR keyword in the *.prm file and add the next few vectors. By default VECTOR 0 is defined (Power on reset vector at 0xFFFE) so add VECTOR 1 for 0xFFFC etc.
You can also create a table in C like the XGATE vector table. I see you have tried this with the table in AN2883 - have a look at the example in AN3015 for file vector_s12x.c as that fits the S12XD. You need to place this table in memory at address 0xFF00 and make sure that all the functions in the table are in near memory so that the compiler only assigns 16bit addresses (rather than 24bit addresses).

Quote:

I guess I'm in general a bit confused on the vector table/base and how the CPU redirects an interrupt to the appropriate Handler (normally, you don't have to do anything other than enable interrupts and create the PIT0_ISR function, but implementing all the code to route to the XGATE, something seems to change and I'm not quite sure what's going on...).

That behaviour hasn't changed. The difference is that you can now optionally send each interrupt individually to XGATE using the RQST bit for each channel. If you don't change the default condition the interrupt will go to the CPU in exactly the same way as you describe. I think there is another issue that is causing the problem because you seem to have vectors in order.

Quote:

When trying to use the vector table from AN2883SW.zip, I get this linking error: Vector allocated at absolute addres 0xFFFE overlaps with sections placed in segment .absSeg648

Yeah, I think you still have the VECTOR 0 directive in the .prm file so the linker is putting your table in the vector space but also being told to put _Startup at address 0xFFFE. It's probably best to remove the VECTOR 0 directive and use the table since then everything is together. Once you do that check that the vector table contains what you expect.

Posted: Tue Jan 17, 2006 6:46 am

Removing the Vector 0 directive did the trick. Thanks for your help - it cleared a lot of things up for me!

Posted: Tue Jan 17, 2006 9:08 am

I'm glad that I could help. Let us know if you run into any more issues setting the part up.

Message Edited by RChapman on 01-27-2006 10:35 PM

topic Interrupts in XGATE and CPU in S12 / MagniV Microcontrollers

Interrupts in XGATE and CPU