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    <title>topic Route Interrupt to XGATE in S12 / MagniV Microcontrollers</title>
    <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/Route-Interrupt-to-XGATE/m-p/125110#M250</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;SPAN style="color: #ff0000;"&gt;This message contains an entire topic ported from a separate forum. The original message and all replies are in this single message. We have seeded this new forum with selected information that we expect will be of value to you as you search for answers to your questions.&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN class="postdetails"&gt;&lt;STRONG&gt;Posted: Mon Nov 14, 2005 11:58 am&lt;SPAN class="gen"&gt;&amp;nbsp;&lt;/SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&lt;/STRONG&gt;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN class="postdetails"&gt;&lt;/SPAN&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN class="postdetails"&gt;&lt;SPAN class="postbody"&gt;Hello everbody,&lt;BR /&gt;&lt;BR /&gt; am I right in thinking that only 8 interrupts in a row can be routet to the xgate? I think that this is not clearly verbalised in the documentation for the Controller.&lt;BR /&gt; If I'm wrong, how can the Interrupts (for example ATD0, PortH and SCI2) be routed to the XGATE?&lt;BR /&gt;&lt;BR /&gt; TIA&lt;BR /&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN class="postdetails"&gt;&lt;SPAN class="postbody"&gt;&lt;SPAN class="postdetails"&gt;&lt;STRONG&gt;Posted: Mon Nov 14, 2005 1:22 pm&lt;SPAN class="gen"&gt;&amp;nbsp;&lt;/SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&lt;/STRONG&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN class="postdetails"&gt;&lt;SPAN class="postbody"&gt;&lt;SPAN class="postdetails"&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN class="postdetails"&gt;&lt;SPAN class="postbody"&gt;&lt;SPAN class="postdetails"&gt;&lt;SPAN class="postbody"&gt;Hi,&lt;BR /&gt; To route any interrupt to the XGate, you just need to set the matching RQST bit of this interrupt.&lt;BR /&gt; You're then free to generate any CPU interrupt when you're finished with the XGate Interrupt treatment.&lt;BR /&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;SPAN class="msg_source_code"&gt;&lt;SPAN class="text_smallest"&gt;Code:&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;PRE&gt;SetIntPrio(0x39, RQST|1);&amp;nbsp;&amp;nbsp; /* assign SW0 interrupt to Xgate, priority 1 */ &lt;/PRE&gt;&lt;DIV&gt;&lt;BR /&gt;&amp;nbsp;&lt;BR /&gt;&lt;SPAN class="postdetails"&gt;&lt;STRONG&gt;Posted: Mon Nov 14, 2005 4:27 pm&lt;SPAN class="gen"&gt;&amp;nbsp;&lt;/SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&lt;/STRONG&gt;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN class="postdetails"&gt;&lt;/SPAN&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN class="postdetails"&gt;maybe the confusion arises because you can only view 8 interrupt setup channels at a time.&lt;BR /&gt; There are multiple banks of 8 registers, so you select the correct page before modifying the register - see Alban's code as an example&lt;BR /&gt; The app note &lt;A _jive_internal="true" href="https://community.nxp.com/external-link.jspa?url=http%3A%2F%2Fwww.freescale.com%2Ffiles%2Fmicrocontrollers%2Fdoc%2Fapp_note%2FAN3144.pdf" rel="nofollow noopener noreferrer" target="_blank"&gt;AN3144&lt;/A&gt; has some explanations and worked examples of this&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN class="postdetails"&gt;&lt;/SPAN&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN class="postdetails"&gt;&lt;SPAN class="postdetails"&gt;&lt;STRONG&gt;Posted: Tue Nov 15, 2005 7:46 am&lt;SPAN class="gen"&gt;&amp;nbsp;&lt;/SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&lt;/STRONG&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN class="postdetails"&gt;&lt;SPAN class="postdetails"&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN class="postdetails"&gt;&lt;SPAN class="postdetails"&gt;&lt;SPAN class="postbody"&gt;Hello,&lt;BR /&gt;&lt;BR /&gt; thanks for your replies. In fact, my problem was I didn't realize that the Interrupt Configuration Data Registers were banked. Now I understand the system.&lt;BR /&gt;&lt;BR /&gt; Thanks&lt;BR /&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Sat, 28 Jan 2006 12:04:18 GMT</pubDate>
    <dc:creator>RChapman</dc:creator>
    <dc:date>2006-01-28T12:04:18Z</dc:date>
    <item>
      <title>Route Interrupt to XGATE</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/Route-Interrupt-to-XGATE/m-p/125110#M250</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;SPAN style="color: #ff0000;"&gt;This message contains an entire topic ported from a separate forum. The original message and all replies are in this single message. We have seeded this new forum with selected information that we expect will be of value to you as you search for answers to your questions.&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN class="postdetails"&gt;&lt;STRONG&gt;Posted: Mon Nov 14, 2005 11:58 am&lt;SPAN class="gen"&gt;&amp;nbsp;&lt;/SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&lt;/STRONG&gt;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN class="postdetails"&gt;&lt;/SPAN&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN class="postdetails"&gt;&lt;SPAN class="postbody"&gt;Hello everbody,&lt;BR /&gt;&lt;BR /&gt; am I right in thinking that only 8 interrupts in a row can be routet to the xgate? I think that this is not clearly verbalised in the documentation for the Controller.&lt;BR /&gt; If I'm wrong, how can the Interrupts (for example ATD0, PortH and SCI2) be routed to the XGATE?&lt;BR /&gt;&lt;BR /&gt; TIA&lt;BR /&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN class="postdetails"&gt;&lt;SPAN class="postbody"&gt;&lt;SPAN class="postdetails"&gt;&lt;STRONG&gt;Posted: Mon Nov 14, 2005 1:22 pm&lt;SPAN class="gen"&gt;&amp;nbsp;&lt;/SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&lt;/STRONG&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN class="postdetails"&gt;&lt;SPAN class="postbody"&gt;&lt;SPAN class="postdetails"&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN class="postdetails"&gt;&lt;SPAN class="postbody"&gt;&lt;SPAN class="postdetails"&gt;&lt;SPAN class="postbody"&gt;Hi,&lt;BR /&gt; To route any interrupt to the XGate, you just need to set the matching RQST bit of this interrupt.&lt;BR /&gt; You're then free to generate any CPU interrupt when you're finished with the XGate Interrupt treatment.&lt;BR /&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;SPAN class="msg_source_code"&gt;&lt;SPAN class="text_smallest"&gt;Code:&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;PRE&gt;SetIntPrio(0x39, RQST|1);&amp;nbsp;&amp;nbsp; /* assign SW0 interrupt to Xgate, priority 1 */ &lt;/PRE&gt;&lt;DIV&gt;&lt;BR /&gt;&amp;nbsp;&lt;BR /&gt;&lt;SPAN class="postdetails"&gt;&lt;STRONG&gt;Posted: Mon Nov 14, 2005 4:27 pm&lt;SPAN class="gen"&gt;&amp;nbsp;&lt;/SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&lt;/STRONG&gt;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN class="postdetails"&gt;&lt;/SPAN&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN class="postdetails"&gt;maybe the confusion arises because you can only view 8 interrupt setup channels at a time.&lt;BR /&gt; There are multiple banks of 8 registers, so you select the correct page before modifying the register - see Alban's code as an example&lt;BR /&gt; The app note &lt;A _jive_internal="true" href="https://community.nxp.com/external-link.jspa?url=http%3A%2F%2Fwww.freescale.com%2Ffiles%2Fmicrocontrollers%2Fdoc%2Fapp_note%2FAN3144.pdf" rel="nofollow noopener noreferrer" target="_blank"&gt;AN3144&lt;/A&gt; has some explanations and worked examples of this&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN class="postdetails"&gt;&lt;/SPAN&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN class="postdetails"&gt;&lt;SPAN class="postdetails"&gt;&lt;STRONG&gt;Posted: Tue Nov 15, 2005 7:46 am&lt;SPAN class="gen"&gt;&amp;nbsp;&lt;/SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&lt;/STRONG&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN class="postdetails"&gt;&lt;SPAN class="postdetails"&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN class="postdetails"&gt;&lt;SPAN class="postdetails"&gt;&lt;SPAN class="postbody"&gt;Hello,&lt;BR /&gt;&lt;BR /&gt; thanks for your replies. In fact, my problem was I didn't realize that the Interrupt Configuration Data Registers were banked. Now I understand the system.&lt;BR /&gt;&lt;BR /&gt; Thanks&lt;BR /&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sat, 28 Jan 2006 12:04:18 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/Route-Interrupt-to-XGATE/m-p/125110#M250</guid>
      <dc:creator>RChapman</dc:creator>
      <dc:date>2006-01-28T12:04:18Z</dc:date>
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