IOC timer0/1 channels overflow flag

UmaMaheswaraReddy — Wed, 09 Oct 2024 17:53:23 GMT

Hi,

Micro: S12ZVCA192

For TIM 0/1 channels timer overflow, TFLG2 TOF flag will get set. If we enable multiple channels of TIM0/1 at a time, How to find TFLG2 TOF flag is set because of which channel timer overflow?

Re: IOC timer0/1 channels overflow flag

lama — Thu, 10 Oct 2024 18:33:37 GMT

Hi,

Table 1-13. Interrupt Vector Locations (Reference Manual)

Vector base + 0x1AC TIM0 timer overflow I bit TIM0TSCR2 (TOF) No Yes

Vector base + 0x08C TIM1 timer overflow I bit TIM1TSCR2 (TOF) No Yes

As you can see different vector number is used for the channels.

Moreover, 0x000F is an offset for the register TFLG2 for each timer.

Exact address can be found:

For

TIM0: chapter: M.11 0x05C0-0x05EF TIM0

TIM1: chapter M.8 0x0400-0x042F TIM1

If you use code warrior you van also check header file to get definition of the registers for given timer.

Best regards,

Ladislav

S12 / MagniV MicrocontrollersのトピックRe: IOC timer0/1 channels overflow flag

IOC timer0/1 channels overflow flag

Re: IOC timer0/1 channels overflow flag