S12 / MagniV MicrocontrollersのトピックRe: DEVKIT-S12ZVC SENTTX bus clock rate

DEVKIT-S12ZVC SENTTX bus clock rate

UmaMaheswaraReddy — Wed, 11 Sep 2024 17:53:52 GMT

Unable to find the information related to SENT clock , SENTTX bus clock rate.

Do we have any external oscillator in the DEVKIT-S12ZVC Evaluation board? How much internal oscillator clock frequency (Fosc) in the Eval board?

What is the SENTTX bus clock rate with below PLL configuration?

In the example code PLL is initialized with below configuration.

/********************************************/
/************ PLL INITIALIZATION ************/
/********************************************/
CPMUCLKS_PLLSEL = 1; //FBUS = FPLL/2. FBUS = 32MHz,
CPMUREFDIV_REFFRQ = 1; //Reference clock between 2MHZ and 6MHZ.
CPMUREFDIV_REFDIV = 0x1; //FREF=8/(1+1) = 4MHZ
CPMUSYNR_VCOFRQ = 0x1; //FVCO is between 48MHZ and 80MHZ
CPMUSYNR_SYNDIV = 0x7; //FVCO = 2xFREFx(SYNDIV+1) = FVCO = 2x4x(7+1) = 64MHZ
CPMUPOSTDIV_POSTDIV = 0x0;//FPLL = FVCO/(POSTDIV+1). FPLL = 64MHZ/(0+1) FPLL = 64MHz
CPMUOSC_OSCE = 1; //External oscillator enable. 8MHZ. FREF=FOSC/(REFDIV+1)
while(!CPMUIFLG_LOCK){} // Wait for LOCK.
CPMUIFLG = 0xFF; // clear CMPMU flags

Re: DEVKIT-S12ZVC SENTTX bus clock rate

lama — Fri, 13 Sep 2024 08:44:54 GMT

Hi,

The MCU can be clocked for either internal or external oscilátor. The internal oscilátor is 1MHz in this devices family and i tis default configuration after reset. The default bus clock is 6.25MHz but you can change it by PLL setup.

PLL calculator.. https://community.nxp.com/t5/S12-MagniV-Microcontrollers/MagniV-PLL-Calculator/ta-p/1104351

Examples…

Chapter 8.7.3 Application Information for PLL and Oscillator Startup in the reference manual

https://community.nxp.com/t5/S12-MagniV-Microcontrollers/S12ZVM-clock-module-and-PLL-configuration-SW-examples/ta-p/1101045

https://community.nxp.com/t5/S12-MagniV-Microcontrollers/S12ZVL-PLL-configuration-with-CPMUPLL/m-p/877617

Best regards,

Ladislav

Re: DEVKIT-S12ZVC SENTTX bus clock rate

UmaMaheswaraReddy — Fri, 13 Sep 2024 10:37:45 GMT

Hi Ladislav,

Thank you for the PLL info.

Below PLL code is from NXP example code (DEVKIT S12ZVC). As per below code bus clock is set to 32MHZ (FBUS = FPLL/2 = 64MHZ/2 = 32MHZ) correct?

SENT TX bus clock is nothing but bus clock (FBUS) correct?

/********************************************/

Our requirement is to set SENT tick rate to 3us (3 microseconds). Is my below understanding correct? If not please let us know how to calculate SENT TX tick rate.

SENT TX tick rate in frequency -> 1/3us-> 333,333.3333333333Hz

SENT TX bus clock = 32MHZ (FBUS)

Our assumption is SENT TX bus clock is nothing but bus clock (FBUS).

SENTTX tick rate = SENTTX bus clock rate / (PRE+1)

PRE+1 = SENT TX bus clock rate/SENT TX tick rate

= 32MHZ/333,333.3333333333HZ

= 96

PRE = 96-1

PRE = 95

If we set PRE to 95 then SENT TX tick rate is set to 3us correct?

Re: DEVKIT-S12ZVC SENTTX bus clock rate

lama — Tue, 17 Sep 2024 13:18:05 GMT

Hi,

yes, you are right for given busclk and required tic time.

BTW, I am not going to think about BUSCLK setup because I do not know wheter you use internal or external oscillator and whether you use PEI, PEE or PBE mode.

Best regards,

Ladislav

Re: DEVKIT-S12ZVC SENTTX bus clock rate

UmaMaheswaraReddy — Wed, 18 Sep 2024 07:14:55 GMT

Hi Ladislav,

We are using S12ZVC-DEVKIT. As per the S12ZVC-DEVKIT schematic we are using external 8MZ oscillator.

Below is the NXP provided sample code. If we flash below code after enabling external oscillator software is entering unknown state. Could you please help us in this? We want to set FBUS 32MHZ clock using PLL.

Re: DEVKIT-S12ZVC SENTTX bus clock rate

danielmartynek — Wed, 18 Sep 2024 10:28:33 GMT

Hi @UmaMaheswaraReddy,

The BUSCLK can be measured at ECLK (PT7).

If you use the values from the PLL calculator:

https://community.nxp.com/t5/S12-MagniV-Microcontrollers/MagniV-PLL-Calculator/ta-p/1104351

And check the registers after configuration, you should measure 32MHz BUS_CLK at ECLK.

Note that 32MHz is the max. allowed BUS_CLK freq at Tj < 150C.

Regards,

Daniel

Re: DEVKIT-S12ZVC SENTTX bus clock rate

UmaMaheswaraReddy — Wed, 18 Sep 2024 11:08:38 GMT

Hi Daniel,

Same settings I used as per the PLL calculator.

Immediately after executing statement "CPMUOSC_OSCE = 1;" software entering unknown state.

Re: DEVKIT-S12ZVC SENTTX bus clock rate

danielmartynek — Thu, 19 Sep 2024 12:55:12 GMT

Hello @UmaMaheswaraReddy,

I just tested the attached project on S12ZVC128 DEVKIT with 8MHz XTAL.

I measure 32MHz at ECLK (PT7).

Can you test it on your side?

Regards,

Daniel

Re: DEVKIT-S12ZVC SENTTX bus clock rate

UmaMaheswaraReddy — Mon, 23 Sep 2024 09:32:58 GMT

Hi,

Sorry for the delay in response.

I am using S12ZVC-DEVKIT. I selected micro as S12ZVCA192.

Same issue with the attached software also.

Re: DEVKIT-S12ZVC SENTTX bus clock rate

danielmartynek — Wed, 25 Sep 2024 11:25:36 GMT

Hi @UmaMaheswaraReddy,

What do you see in the registers of the S12ZMMCV1 module when this happens?

Are all the interrupt routines implemented in the project.

Refer to this interrupt catcher:

https://community.nxp.com/t5/S12-MagniV-Microcontrollers/S12Z-Interrupt-catcher-for-unexpected-interrupts/ta-p/1117675

Is there a machine exception rising?

Regards,

Daniel