s12zvl128

AsaZJP — Thu, 18 Apr 2024 08:33:28 GMT

Hi Supporters：

We found a problem while testing LIN bit error that I can't understand for the time being, and need your help The chip we use is the S12ZVL128 chip;

Test Steps

Test prerequisites: The LIN signal 0x27 data outgoing from the MCU are: 0x01, 0x00, 0x24, 0x08, 0x00, 0x00, 0x00, 0x00 When the stop bit of the outgoing signal 0x27 is disturbed, the value of the BERRIF bit of the register SCI Alternative Status Register 1 (SCIASR1) is detected, Set the value of the signal in the 0x27 LINError_SSM_R_BCM_LIN1;

Test:

1. Send 0x27 signal normally

2. Use the built-in interference function dword linInvertRespBit (long frameID, dword byteIndex, dword bitIndex) in Canoe to interfere with the stop bit of byte6 of 0x27

Expected Result: The value of the BERRIF bit of the SCI Alternative Status Register 1 (SCIASR1) was detected to be 1, and the signal of the LINError_SSM_R_BCM_LIN1 in the 0x27 was 1;

Actual Results: The value of the BERRIF bit of the register SCI Alternative Status Register 1 (SCIASR1) was detected to be 0, and the signal of the LINError_SSM_R_BCM_LIN1 in the 0x27 was detected to be 0;

3. Use the built-in interference function dword linInvertRespBit (long frameID, dword byteIndex, dword bitIndex) in Canoe to interfere with the stop bit of byte3 of 0x27

Expected Result: The value of the BERRIF bit of the SCI Alternative Status Register 1 (SCIASR1) was detected to be 1, and the signal of the LINError_SSM_R_BCM_LIN1 in the 0x27 was 1;

Actual Results: The value of the BERRIF bit of the register SCI Alternative Status Register 1 (SCIASR1) was detected to be 1, and the value of the signal of the LINError_SSM_R_BCM_LIN1 in the 0x27 was 1;

And regardless of byte3 or byte6 of the interference 0x27, the data transmission of 0x27 is aborted, but the data of 0x27 is all 0x00 stop bits, and the value of the BERRIF bit of register SCI Alternative Status Register 1 (SCIASR1) is 0 when it is interfered with The value of the BERRIF bit of the register SCI Alternative Status Register 1 (SCIASR1) is 1 when the data of the 0x27 is not all 0 is disturbed.

Why can't I set the BERRIF bit of the SCI Alternative Status Register 1 (SCIASR1) when the stop bit of the data is disturbing the data?

BR,

Asa

S12 / MagniV Microcontrollersのトピックs12zvl128

s12zvl128