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    <title>S12 / MagniV MicrocontrollersのトピックMultiple interrupts</title>
    <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/Multiple-interrupts/m-p/1610568#M19105</link>
    <description>&lt;P&gt;Hi Team,&lt;/P&gt;&lt;P&gt;I am using S12Z family MCU, in that when a two bit RAM/EEPROM error occurs the MCU enters Machine exception ISR. I am attaching the file used to generate two bit RAM error&lt;/P&gt;&lt;P&gt;I want to show that a two bit error has occurred on GUI(which is not happening once it entered machine exception ISR) , I am using SCI0 ISR as communication interrupt.&lt;/P&gt;&lt;P&gt;How does MCU treats when multiple interrupts requests occurs at same time and I would also like to know if SCI interrupt can be given higher priority than machine exception.&lt;/P&gt;</description>
    <pubDate>Tue, 07 Mar 2023 05:35:31 GMT</pubDate>
    <dc:creator>kathi</dc:creator>
    <dc:date>2023-03-07T05:35:31Z</dc:date>
    <item>
      <title>Multiple interrupts</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/Multiple-interrupts/m-p/1610568#M19105</link>
      <description>&lt;P&gt;Hi Team,&lt;/P&gt;&lt;P&gt;I am using S12Z family MCU, in that when a two bit RAM/EEPROM error occurs the MCU enters Machine exception ISR. I am attaching the file used to generate two bit RAM error&lt;/P&gt;&lt;P&gt;I want to show that a two bit error has occurred on GUI(which is not happening once it entered machine exception ISR) , I am using SCI0 ISR as communication interrupt.&lt;/P&gt;&lt;P&gt;How does MCU treats when multiple interrupts requests occurs at same time and I would also like to know if SCI interrupt can be given higher priority than machine exception.&lt;/P&gt;</description>
      <pubDate>Tue, 07 Mar 2023 05:35:31 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/Multiple-interrupts/m-p/1610568#M19105</guid>
      <dc:creator>kathi</dc:creator>
      <dc:date>2023-03-07T05:35:31Z</dc:date>
    </item>
    <item>
      <title>Re: Multiple interrupts</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/Multiple-interrupts/m-p/1611019#M19107</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;could you please check following thread which contains example code....&lt;/P&gt;
&lt;P&gt;&lt;A href="https://community.nxp.com/t5/S12-MagniV-Microcontrollers/Single-double-bit-RAM-ECC-error-example-code-at-S12ZVC/ta-p/1123379" target="_blank"&gt;https://community.nxp.com/t5/S12-MagniV-Microcontrollers/Single-double-bit-RAM-ECC-error-example-code-at-S12ZVC/ta-p/1123379&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;Next thing, I would like to ask what was not clear in the answer for multiply interrupts &lt;A href="https://community.nxp.com/t5/S12-MagniV-Microcontrollers/Multiple-Interrupt/td-p/1609854" target="_blank"&gt;https://community.nxp.com/t5/S12-MagniV-Microcontrollers/Multiple-Interrupt/td-p/1609854&lt;/A&gt;&amp;nbsp; .&lt;/P&gt;
&lt;P&gt;Best regards,&lt;/P&gt;
&lt;P&gt;Ladislav.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Tue, 07 Mar 2023 15:40:18 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/Multiple-interrupts/m-p/1611019#M19107</guid>
      <dc:creator>lama</dc:creator>
      <dc:date>2023-03-07T15:40:18Z</dc:date>
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