S12 / MagniV MicrocontrollersのトピックRe: S12ZVM ADC timing and data consistency

S12ZVM ADC timing and data consistency

lill1990 — Wed, 07 Sep 2022 09:35:19 GMT

Dear sir,

I have a code fragment as below in my application.

/*****************************************************************/

ADC0FLWCTL_RSTA = 1u;

while (ADC0CONIF_1_EOL_IF == 0u)
{
//_asm("NOP");
Variable1= ADCResult[0]; /*read data from RVL*/
Variable2= ADCResult[1];
}

/*****************************************************************/

When the loop is exited(all ADC commands were completed, EOL_IF was set), I could get valid Variable1, however, the Variable2 was mostly invalid.

I inserted a "NOP" to the loop, then I could get all data.

I suspect it is caused by ADC timing and data consistency, but I don't have a clear understanding about that.

Could you tell me the probably reason behind this ?

Thanks very much.

Re: S12ZVM ADC timing and data consistency

danielmartynek — Thu, 08 Sep 2022 06:34:38 GMT

Hello @lill1990,

As per the EOL_IF description, this bit is set by the binary coded conversion command type select bits CMD_SEL[1:0] for “end of list” type of commands and after such a command has been processed and the related data has been stored RAM.

Can you share the whole ADC configuration?

Or a test project so that I can reproduce the error?

Thank you,

BR, Daniel

Re: S12ZVM ADC timing and data consistency

lill1990 — Thu, 08 Sep 2022 07:24:56 GMT

Hello Daniel,

Thanks very much for your reply.

I attached the code and hope it is helpful for you.

Re: S12ZVM ADC timing and data consistency

danielmartynek — Thu, 08 Sep 2022 09:30:59 GMT

Thank you for the code.

I see you use the max specified BUS_CLK freq (50MHz) and ADCCLK freq (8.33MHz).

Which PLL mode do you use?

Are you sure the BUS_CLK = 50MHz?

Can you scope the clock at ECLK?

Is PLL modulation enabled (CPMUPLL)?

Thanks,

Daniel

Re: S12ZVM ADC timing and data consistency

lill1990 — Fri, 09 Sep 2022 06:00:53 GMT

Hello Daniel.

IRC is used in my application and I am sure the clock is correct.

PLL frequency modulation is off.

Thanks.

Re: S12ZVM ADC timing and data consistency

danielmartynek — Fri, 09 Sep 2022 11:40:07 GMT

Hi @lill1990,

I will need to test it.
What is the part number of the MCU (mask-set)?

From the code, I see that you measure the VSUP only if VSUP < 4.5V
Have you tested it under normal conditions when VSUP =~12V.

Since the measurement takes place at low supply voltage, is the BUS_CLK (ADC_CLK) stabilized at the time of the measurement?

Thanks,
Daniel

Re: S12ZVM ADC timing and data consistency

lill1990 — Fri, 09 Sep 2022 14:55:13 GMT

Hello Daniel,

The MCU is MC9S12ZVML31, mask set 1N14N.

Yes, the code is used in the initialization to ensure the VSUP is >=4.5 before starting GDU.

The VSUP was stable as 12V, I reset MCU to test this function via debugger.

I tried to add a breakpoint into the while{ADC0CONIF_1_EOL_IF == 0u} loop, then continue running, every thing was OK. I think the ADC completed the conversation during the break.

But if no any break before EOL flag was set by HW, the behavior I described in this question will appear.

Thanks.

Re: S12ZVM ADC timing and data consistency

danielmartynek — Tue, 20 Sep 2022 14:36:35 GMT

Hello @lill1990,

I'm sorry for the delay, I was out of office for a few days and could not test it earlier.

I'm not able to reproduce the issue with the test code attached.

Can you run the test project on your side?

BR, Daniel