4 Layer vs 2 layer for MC9S12E128

khumphri — Fri, 27 Jan 2006 14:43:56 GMT

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Posted: Thu Dec 8, 2005 12:35 pm

To all:

I am the recent Pierce Osc Problem person. Prob resloved by reading old postings 2004 from ____ to a guy with exact same problem and sysymptoms. Thanks again ____. Pierce Osc works perfectly now.

Now that we have solved the Pierce Osc problem by correctly connecting VDD1 and VDD2, I need to redesign the pcb.

Over the past year when I was doing noise testing on the product I found the part was VERY sensitive to resetting. VERY. But, this was with:

1) the VDD1 and VDD2 connected directly to VDD

2) 2 layer pcb

3) colpitts osc - the only one that would run

4) much of the VDD, GROUND, PLL, XTAL pcb layout closer to a PIC design layout than the exact layout suggestions that are in the current Freescale app notes and the MC9S12E128 design guide - released 10/2005

When I switched to a 4 layer PCB the resetting went away. With all the above mistakes.

This is my question: If I follow the pcb layout rules on a 2 layer PCB exactly is there much to be gained by adding a 4 layer pcb? Our device is powered by an isolated class2 xfmr, lots of bypass caps, 7805 5V regulator, big electrolitic cap before the regulator.

If it has significant value then I'll do the 4 layer PCB, but if the experienced users out there tell me that if the pcb is done correctly with 2 layers then 4 layer should not be necessary, then I'll do that. So guys - what do I do?

Posted: Thu Dec 8, 2005 1:02 pm

My personal opinion based on my experience: Any modern digital microcontroller circuit running above 4MHz bus speed should be better designed with 4 layers as a minimum. That is 2 layers minimum for power and GND, and 2 layers minimum for routing. If there is a lot of routing, even more than 2 routing layer are needed. If there are more than 1 primary power supply (for example in mixed 5V, 3.3V, 2.5V designs) an even higher number of power planes are needed.

The noise is just significantly reduced when you have solid GND and power plane - well worth the extra PCB cost, according to my experience.

Posted: Thu Dec 8, 2005 1:22 pm

I agree in principal on the 4 layer is better the 2 layer (substitute feet sounds like Animal Farm). In practice what ever you do look at the Freescale PCB layout example, and keep tracks and ground planes away from under the crystal, and have a single point connection to 0V. In practice I have followed these rules but in two layer board with a ground plane, and the processor runs perfectly. Obviously spend some time de-fragmenting the ground plane in your PCB design if do use two layer PCB.

Posted: Thu Dec 8, 2005 1:43 pm

>I am the recent Pierce Osc Problem person. Prob resloved by reading

>old postings 2004 from ______ to a guy with exact same problem and

>sysymptoms. Thanks again _____. Pierce Osc works perfectly now.

>Now that we have solved the Pierce Osc problem by correctly connecting

>VDD1 and VDD2, I need to redesign the pcb.

I also at one time designed a board that had VDD1 and VDD2 connected to 5 Volts. Luckily I saw a posting on this list where someone else had done the same thing before I had the boards stuffed. It is confusing the way the pins are labeled.

With regard to the oscillator circuits, I have always used a prepackaged oscillator IC such as the Epson SG-636PCE and have never had any problems at all. I have never understood the benefit of using the discrete component design. Is it a cost issue?

Posted: Thu Dec 8, 2005 2:15 pm

>With regard to the oscillator circuits, I have always used a prepackaged

>oscillator IC such as the Epson SG-636PCE and have never had any

>problems at all. I have never understood the benefit of using the

>discrete component design. Is it a cost issue ?

Sometimes, but then we are usually using something other than an HC12-family. The bigger issue is usually power. The standard "discrete part" design allows for MUCH lower power consumption. [Not untypical project - run the board for a minimum of 4 years on 4 AA batteries, with a goal of 8 years. That means a standard oscillator package draws about a thousand times more power than our total power budget.]

Posted: Thu Dec 8, 2005 1:47 pm

The noise is just significantly reduced when you have solid GND and power plane - well worth the extra PCB cost, according to my experience.

Posted: Thu Dec 8, 2005 2:44 pm

If I use a 4 layer pcb do I still have to make the gound on the top signal layer be like the Freescale drawingsd? What does "and have a single point connection to 0V" mean? I am confused about the rigid layout drawing giving in the Freescale manual. It seems to me like having a full ground plane layer sort of wipes out any star type ground-star type layout on the top layer - like the one shown in the pictures. So should I try to draw the top layer ground traces just like the picture - even though there is a ground plane underneath? And if so where do I connect the ground plane to the signal plane ground? On my pcb all the PLL and OSC components and all the bypass capacitors are "through-hole" so there are ground connections between the top layer and the ground plane layer all over the place - where ever there is a through hole ground pin. Note: I used the Colpitts for the first 100 PCB.s and am going to switch to the Pierce for the next round.

Posted: Thu Dec 8, 2005 3:32 pm

All our HC12 designs have used 4 layer pcbs. We had noise issues on some 2 layer HC08 boards - a 4 layer redesign fixed the issues.

I have never used the ground layout suggested in the Freescale datasheets on our 4 layer boards. We have several compact boards with 112 pin parts and need the area under the micro for routing and signal vias.

In our designs every power and ground pin on the micro gets a short 0.4 or 0.5mm wide trace and via to the planes - often the via is nearly touching the end of the pad. Bypass capacitors get their own traces/vias to the plane (we use SMT parts but you get the same effect using thru-hole parts). We sometimes route a bypass capacitor right to the pin when space gets a little tight and a separate via for the cap doesn't fit.

Advice I received from a few ESD/EMI experts - never put a split in a ground plane until you prove that a solid/single plane has a problem.

Another small thing I do is move vias around slightly when the thermal relief of 3 or more vias touch on the ground plane. 3 vias touching = split in ground plane in my book.

Posted: Thu Dec 8, 2005 3:33 pm

I could have been clearer. I use the colpits oscillator. When I design four layer PCBs the power planes are internal and the tracking on the outer surfaces. Putting the planes inside is done to prevent warping when heating the board to solder it, and putting the tracks on the outer sides allows you to fault find more easily. The single point 0V is only for the crystal and the pll, and forms a star which is connected at one point to 0V and the ground plane.

The Freescale example (as in my own case) does not have ground plane or any other signal under the oscillator, and I have the pll next to the crystal also with no ground plane or other signal under it. Therefore you should not have ground plane underneath, like an island of no planes or signal lines in a sea of planes and signals. You don't need a plane on the top layer for the crystal and pll, but of cause if you need it for your design add it as shown in the Freescale example.

Posted: Thu Dec 8, 2005 4:05 pm

Thanks everyone for your design advice. I will implement it now.

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4 Layer vs 2 layer for MC9S12E128