About S12Z ADC sample time and interrupt

jx1207 — Fri, 13 Mar 2020 07:03:01 GMT

1.ADC saple time

the above figure as the example ,8-bit data,4 cycle sampling , the adc min sampling time=?

the adc sampling time =adc clock/12 or 13? if is 13,why?

2.ADC Interrupt

If I want trigger the adc interrupt by timer0,every 50ms sample the data 100times by AN3,how to do it ?

The INTFLG[3:0] is to configure the interrupt flag number(1~15),the interrupt flag number is defined by myself? If I want to sample the AN3,can I set the interrupe flag number is 1 or 2,...?

Re: About S12Z ADC sample time and interrupt

danielmartynek — Sun, 15 Mar 2020 18:55:33 GMT

Hello jx1207@126.com,

1.
You didn’t specify the MagniV device.
Let’s take S12ZVL.
The ATD conversion time is specified in Table C-1, S12ZVL RM rev2.48

In the Figure 28-10 example:
Sample time: 4 ATD clock cycles
Hold time: 12 ATD clock cycles
Conversion time: 16 ATD clock cycles.

2.
Please have a look at Example S12ZVL ADC0 triggered by TIM0 OC updates PWM duty cycle

It uses TIM0 Output Capture on Ch2 to trigger an ADC sequence periodically.

Please see the description of the ADC command registers in the RM.
In ADCCMD_1[CH_SEL[5:0]] you can select AN3.
In ADCCMD_0[INTFLG_SEL[3:0]] you can select which interrupt flag is set in the ADCIFH/L register
at the end of this conversion.

Regards,

Daniel

S12 / MagniV MicrocontrollersのトピックAbout S12Z ADC sample time and interrupt

About S12Z ADC sample time and interrupt

Re: About S12Z ADC sample time and interrupt