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    <title>topic Re: How to generate PLL lock reset for S12/MagniV in S12 / MagniV Microcontrollers</title>
    <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/How-to-generate-PLL-lock-reset-for-S12-MagniV/m-p/963932#M16782</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;Unfortunately, there is no way for the user to trigger the PLL clock monitor reset (PMRF).&lt;BR /&gt;It is a safety feature and only for the case that the PLL is really damaged.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;BR, Daniel&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 26 Jun 2019 11:24:28 GMT</pubDate>
    <dc:creator>danielmartynek</dc:creator>
    <dc:date>2019-06-26T11:24:28Z</dc:date>
    <item>
      <title>How to generate PLL lock reset for S12/MagniV</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/How-to-generate-PLL-lock-reset-for-S12-MagniV/m-p/963931#M16781</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi All,&lt;/P&gt;&lt;P&gt;I am using MC9S12ZVLA128 micro for my application. I am using external 10MhZ clock crystal.&lt;/P&gt;&lt;P&gt;And I have used the OMRE(Oscillator monitor Reset Enable) feature of the MCU.&lt;/P&gt;&lt;P&gt;As a part of my application feature, I have to write one pattern to EEPROM after getting restart from PLL lock reset based on the status of the reset flag register.&lt;/P&gt;&lt;P&gt;Here I want to test my code by reproducing the scenario that causes the PLL lock reset. I am not sure how to reproduce the PLL lock reset.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Can you help me on this with any test code or other steps to test my application software.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Vyshakh J&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 24 Jun 2019 14:37:17 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/How-to-generate-PLL-lock-reset-for-S12-MagniV/m-p/963931#M16781</guid>
      <dc:creator>vyshakh_j</dc:creator>
      <dc:date>2019-06-24T14:37:17Z</dc:date>
    </item>
    <item>
      <title>Re: How to generate PLL lock reset for S12/MagniV</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/How-to-generate-PLL-lock-reset-for-S12-MagniV/m-p/963932#M16782</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;Unfortunately, there is no way for the user to trigger the PLL clock monitor reset (PMRF).&lt;BR /&gt;It is a safety feature and only for the case that the PLL is really damaged.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;BR, Daniel&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 26 Jun 2019 11:24:28 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/How-to-generate-PLL-lock-reset-for-S12-MagniV/m-p/963932#M16782</guid>
      <dc:creator>danielmartynek</dc:creator>
      <dc:date>2019-06-26T11:24:28Z</dc:date>
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