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    <title>S12 / MagniV Microcontrollersのトピックnot able to update SPI0DR</title>
    <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/not-able-to-update-SPI0DR/m-p/959173#M16733</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I am using SPI0 on S12ZVLA128. I tried to do send and receive in polling mode. the SPI is in slave mode.&amp;nbsp;I am checking the SPI0SR register every 10ms. The issue is the SPTEF never set, although I can see there is data on the MISO line. Since the SPTEF never set, I cannot update the SPI0DR. The MISO is sending what ever received on MOSI.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Are you able to help? thanks, Ke&amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 08 Oct 2019 20:44:13 GMT</pubDate>
    <dc:creator>kelimagna</dc:creator>
    <dc:date>2019-10-08T20:44:13Z</dc:date>
    <item>
      <title>not able to update SPI0DR</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/not-able-to-update-SPI0DR/m-p/959173#M16733</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I am using SPI0 on S12ZVLA128. I tried to do send and receive in polling mode. the SPI is in slave mode.&amp;nbsp;I am checking the SPI0SR register every 10ms. The issue is the SPTEF never set, although I can see there is data on the MISO line. Since the SPTEF never set, I cannot update the SPI0DR. The MISO is sending what ever received on MOSI.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Are you able to help? thanks, Ke&amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 08 Oct 2019 20:44:13 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/not-able-to-update-SPI0DR/m-p/959173#M16733</guid>
      <dc:creator>kelimagna</dc:creator>
      <dc:date>2019-10-08T20:44:13Z</dc:date>
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    <item>
      <title>Re: not able to update SPI0DR</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/not-able-to-update-SPI0DR/m-p/959174#M16734</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Ke,&lt;/P&gt;&lt;P&gt;I am not sure what it a root cause in your case. But I have a few points for you.&lt;/P&gt;&lt;OL&gt;&lt;LI&gt;From my point of view, there might be a problem with chip-select (slave select) pin. Is chip-select signal between master and slave used or SS pin is connected to GND at the slave side? Be aware that CPHA=0 mode (data sampling at first SCK edge) is not compatible with static slave select pin … The transfer ends by the rising edge at SS pin. Please check correct CPHA bit settings – must be the same as on the master side. Please check also MODFEN and SSOE bits – they should be both log.1 for active slave select input pin.&lt;/LI&gt;&lt;LI&gt;The S12ZVL has only one SPI0 routing option. The SPI0 signals are routed at pins PS0~PS3. However, these pins may be occupied also by higher priority signals like ECLK, Timer, CAN, SCI, PWM signals. Please check Table 2-1. Pin Functions and Priorities in RM and MODRR0~MODRR3 routing register settings for avoiding routing issues. Be aware that MODRR0~3 register could be written just once in normal mode – all configuration must be written by single register write command.&lt;BR /&gt; The ECLK signal may be enabled/disabled in ECLKCTL register.&lt;/LI&gt;&lt;LI&gt;Please check the transfer width at XFRW bit. Set for 16bit transfers. Clear for 8bit (or any other) transfers.&lt;/LI&gt;&lt;LI&gt;Since the SPI module is set as slave, SPI baud rate register value is irrelevant, but you may check whether the maximum SPI baudrate is lower than bus clock/4 (the limit for SPI slave).&lt;/LI&gt;&lt;LI&gt;I suppose that you don’t use bidirectional mode and SPC0 bit is cleared. Correct?&lt;/LI&gt;&lt;/OL&gt;&lt;P&gt;&lt;BR /&gt;I hope it helps you.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Have a great day,&lt;BR /&gt;Radek&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 10 Oct 2019 14:10:20 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/not-able-to-update-SPI0DR/m-p/959174#M16734</guid>
      <dc:creator>RadekS</dc:creator>
      <dc:date>2019-10-10T14:10:20Z</dc:date>
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