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    <title>topic Re: SCI0 &amp; MSCAN0 routing problem in S12 / MagniV Microcontrollers</title>
    <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/SCI0-MSCAN0-routing-problem/m-p/954292#M16665</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;According to Fig. 2-2 MOC0RR2:1 = 11 not only route MSCAN0 to&amp;nbsp;TXCAN0/RXCAN0 pins, but also route CAN PHY CPU side pins to CPTXD0 and CPRXD0 (PS1:0).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I tried toggling PS1:0 GPIO with MOC0RR2:1 set to 11. It works until CANPHY is enabled. So I guess you have CAN PHY enabled and this blocks SCI0 on PS1:0.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Edward&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 06 Aug 2019 11:36:07 GMT</pubDate>
    <dc:creator>kef2</dc:creator>
    <dc:date>2019-08-06T11:36:07Z</dc:date>
    <item>
      <title>SCI0 &amp; MSCAN0 routing problem</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/SCI0-MSCAN0-routing-problem/m-p/954291#M16664</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;I am now using the S12ZVC12F0VKH. I tried to route the TXCAN0/RXCAN0 to pin PS3/2 while at the same time &lt;SPAN&gt;route &lt;/SPAN&gt;TXD0/RXD0 to pin PS1/0. I set the&amp;nbsp;MODRR0_M0C0RR = 0b110 and&amp;nbsp;MODRR0_SCI0RR = 1. When I test on the S12ZVC-DEVKIT, the MSCAN works well while SCI0 does not work. According to&amp;nbsp;the figure 2-2 on S12ZVC_RM.pdf, I wonder if the PS1/2 are routed to&amp;nbsp;CPTXD0/CPRXD0 and can not be routed to SCI0 in the way I set the registers.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 06 Aug 2019 04:15:18 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/SCI0-MSCAN0-routing-problem/m-p/954291#M16664</guid>
      <dc:creator>thulzh</dc:creator>
      <dc:date>2019-08-06T04:15:18Z</dc:date>
    </item>
    <item>
      <title>Re: SCI0 &amp; MSCAN0 routing problem</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/SCI0-MSCAN0-routing-problem/m-p/954292#M16665</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;According to Fig. 2-2 MOC0RR2:1 = 11 not only route MSCAN0 to&amp;nbsp;TXCAN0/RXCAN0 pins, but also route CAN PHY CPU side pins to CPTXD0 and CPRXD0 (PS1:0).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I tried toggling PS1:0 GPIO with MOC0RR2:1 set to 11. It works until CANPHY is enabled. So I guess you have CAN PHY enabled and this blocks SCI0 on PS1:0.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Edward&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 06 Aug 2019 11:36:07 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/SCI0-MSCAN0-routing-problem/m-p/954292#M16665</guid>
      <dc:creator>kef2</dc:creator>
      <dc:date>2019-08-06T11:36:07Z</dc:date>
    </item>
    <item>
      <title>Re: SCI0 &amp; MSCAN0 routing problem</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/SCI0-MSCAN0-routing-problem/m-p/954293#M16666</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thank you. I have do the same test and also succeeded in toggling the PS1:0.&lt;/P&gt;&lt;P&gt;According to this phenomenon, I&amp;nbsp;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;set the&amp;nbsp;MODRR0_M0C0RR = 0b110, MODRR0_SCI0RR = 1 as well as DDRS_DDRS1:0 = 1(configured as output). Then I tried to send out message through SCI0 in PS1:0.&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;After I download the project into S12DEVKIT, I run the project under debug mode (CW11.1) and the MSCAN on PS2/3 and SCI0 on PS1/0 both worked well.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;Then I&amp;nbsp;terminated in the debug mode, unpluged the USB&amp;nbsp;and pressed the reset button to make the MCU work in normal mode. It turned out that the MSCAN still worked well on PS2/3 but the SCI0 did not work well on PS1/0 while SCI0 worked well on PJ0/1.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;The same code has different results in the debug mode and normal mode. How to analyze this problem?&lt;/SPAN&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;Zhenghong&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 06 Aug 2019 12:14:11 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/SCI0-MSCAN0-routing-problem/m-p/954293#M16666</guid>
      <dc:creator>thulzh</dc:creator>
      <dc:date>2019-08-06T12:14:11Z</dc:date>
    </item>
    <item>
      <title>Re: SCI0 &amp; MSCAN0 routing problem</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/SCI0-MSCAN0-routing-problem/m-p/954294#M16667</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;CAN PHY isn't enabled by default in normal mode, and my code to set up MODRR0 then keep toggling works well standalone. But you should make sure CAN PHY isn't enabled by some part of your code.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Since you modified MODRR0, chances are you set up it wrong way. MODRR0 is write once (in normal mode) register, which means you need to write all bits as desired at once. You can't set up MODRR0 bits for CAN routing, then set up SCI0 bit for SCI0 routing. 2nd and further writes are ignored in normal mode.&amp;nbsp;You need to write all MODRR0 bits in the same asm/C instruction.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;What's interesting some MODRR registers are write once and some have unrestricted writes. Next time you project works in debugger and doesn't work standalone you should search through RM to find write once registers and bits in question.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Edward&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 06 Aug 2019 12:36:09 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/SCI0-MSCAN0-routing-problem/m-p/954294#M16667</guid>
      <dc:creator>kef2</dc:creator>
      <dc:date>2019-08-06T12:36:09Z</dc:date>
    </item>
    <item>
      <title>Re: SCI0 &amp; MSCAN0 routing problem</title>
      <link>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/SCI0-MSCAN0-routing-problem/m-p/954295#M16668</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Wonderful! Thanks a lot!&lt;/P&gt;&lt;P&gt;The write once operation solved the problem!&lt;/P&gt;&lt;P&gt;Before this, although I have noticed this note on the RM, I can not understand what it means actually. Now, I get it!&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Zhenghong&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 06 Aug 2019 12:54:47 GMT</pubDate>
      <guid>https://community.nxp.com/t5/S12-MagniV-Microcontrollers/SCI0-MSCAN0-routing-problem/m-p/954295#M16668</guid>
      <dc:creator>thulzh</dc:creator>
      <dc:date>2019-08-06T12:54:47Z</dc:date>
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